Abstract
A novel hardware architecture for memetic vector quantizer (VQ) design is presented in this paper. The architecture uses steady-state genetic algorithm (GA) for global search, and C-means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state GA operations. It also uses a pipeline architecture for the hardware implementation of C-means algorithm. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for VQ optimization attaining both high performance and low computational time.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Choi, Y.H., Chung, D.J.: VLSI Processor of Parallel Genetic Algorithm. In: IEEE Asia Pacific Conf. on ASICs, pp. 143–146 (2000)
Eiben, A.E., Smith, J.D.: Introduction to Evolutionary Computing. Springer, Heidelberg (2003)
Gersho, A., Gray, R.M.: Vector Quantization and Signal Compression. Kluwer, Norwood (1992)
Hwang, W.J., Hong, S.L.: Genetic entropy-constrained vector quantization. Optical Engineering 38, 233–239 (1999)
Hwang, W.J., Li, H.Y., Yeh, Y.J., Chan, K.F.: Book Progress in Neurocomputing Research. In: FPGA Implementation of Competitive Learning with Partial Distance Search in the Wavelet Domain ch. 8, pp. 203–221. NOVA Science Publisher (2008)
Hauck, S., Dehon, A.: Reconfigurable Computing. Morgan Kaufmann, San Francisco (2008)
Mitchell, M.: An introduction to genetic algorithm. MIT press, Cambridge (1996)
Nedjah, N., Mourelle, L.: Hardware Architecture for Genetic Algorithms. In: Ali, M., Esposito, F. (eds.) IEA/AIE 2005. LNCS, vol. 3533, pp. 554–556. Springer, Heidelberg (2005)
Rasheed, K., Davisson, B.D.: Effect of global parallelism on the behave of a steady state genetic algorithm for design optimization. In: Proceedings of the Congress on Evolutionary Computation, Washington, DC (1999)
Tommiska, M., Vuori, J.: Implementation of genetic algorithms with programmable logic devices. In: Proc. 2nd Nordic Workshop on Genetic Algorithms and Their Applications, pp. 111–126 (1996)
Stratix II Device Handbook, Altera Corporation (2008), http://www.altera.com/literature/lit-nio2.jsp
NIOS II Processor Reference Handbook, Altera Corporation (2008), http://www.altera.com/literature/lit-nio2.jsp
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Weng, SK., Ou, CM., Hwang, WJ. (2009). VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware. In: Hua, A., Chang, SL. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2009. Lecture Notes in Computer Science, vol 5574. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03095-6_49
Download citation
DOI: https://doi.org/10.1007/978-3-642-03095-6_49
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-03094-9
Online ISBN: 978-3-642-03095-6
eBook Packages: Computer ScienceComputer Science (R0)