Abstract
This paper presents a parallel ATPG to speed up the test pattern gen- eration process. The ATPG adopts the master-slave architecture to reduce the inter-process communication. Also, a smart fault list broadcast and fault partition technique is proposed to reduce test pattern inflation. Simulation results show that close to linear speed-up can be achieved for up to 7 slave processes.
This work was partially supported by National Science of Taiwan, R.O.C., under Grant No. NSC 96-2221-E-002-275-MY3.
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Yeh, K.W., Wu, M.F., Huang, J.L. (2009). A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method. In: Hua, A., Chang, SL. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2009. Lecture Notes in Computer Science, vol 5574. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03095-6_35
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DOI: https://doi.org/10.1007/978-3-642-03095-6_35
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