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Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects

  • Zhimin Chen
  • Syed Haider
  • Patrick Schaumont
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5576)

Abstract

Hardware masking is a well-known countermeasure against Side-Channel Attacks (SCA). Like many other countermeasures, the side-channel resistance of masked circuits is susceptible to low-level circuit effects. However, no detailed analysis is available that explains how, and to what extent, these low-level circuit effects are causing side-channel leakage. Our first contribution is a unified and consistent analysis to explain how glitches and inter-wire capacitance cause side-channel leakage on masked hardware. Our second contribution is to show that inter-wire capacitance and glitches are causing side-channel leakage of comparable magnitude according to HSPICE simulations. Our third contribution is to confirm our analysis with a successful DPA-attack on a 90nm COMS FPGA implementation of a glitch-free masked AES S-Box. According to existing literature, this circuit would be side-channel resistant, while according to our analysis and measurement, it shows side-channel leakage. Our conclusion is that circuit-level effects, not only glitches, present a practical concern for masking schemes.

Keywords

Power Consumption Average Power Consumption Real Circuit HSPICE Simulation Masking Scheme 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Zhimin Chen
    • 1
  • Syed Haider
    • 1
  • Patrick Schaumont
    • 1
  1. 1.Virginia TechBlacksburgUSA

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