Using Reconfigurable Supercomputers and C-to-Hardware Synthesis for CNN Emulation

  • J. Javier Martínez-Álvarez
  • F. Javier Garrigós-Guerrero
  • F. Javier Toledo-Moreo
  • J. Manuel Ferrández-Vicente
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5602)


The complexity of hardware design methodologies represents a significant difficulty for non hardware focused scientists working on CNN-based applications. An emerging generation of Electronic System Level (ESL) design tools is been developed, which allow software-hardware codesign and partitioning of complex algorithms from High Level Language (HLL) descriptions. These tools, together with High Performance Reconfigurable Computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of CNN-based applications. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, is analyzed. A sequential CNN architecture, suitable for FPGA implementation, proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results for a typical edge detection algorithm shown that, with a minimum development time, a 10x acceleration, when compared to the software emulation, can be obtained.


Parallel Architecture Cellular Neural Network Image Processing Algorithm Communicate Sequential Process FPGA Board 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • J. Javier Martínez-Álvarez
    • 1
  • F. Javier Garrigós-Guerrero
    • 1
  • F. Javier Toledo-Moreo
    • 1
  • J. Manuel Ferrández-Vicente
    • 1
  1. 1.Dpto. Electrónica, Tecnología de Computadoras y ProyectosUniversidad Politécnica de CartagenaCartagenaSpain

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