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Using Reconfigurable Supercomputers and C-to-Hardware Synthesis for CNN Emulation

  • J. Javier Martínez-Álvarez
  • F. Javier Garrigós-Guerrero
  • F. Javier Toledo-Moreo
  • J. Manuel Ferrández-Vicente
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5602)

Abstract

The complexity of hardware design methodologies represents a significant difficulty for non hardware focused scientists working on CNN-based applications. An emerging generation of Electronic System Level (ESL) design tools is been developed, which allow software-hardware codesign and partitioning of complex algorithms from High Level Language (HLL) descriptions. These tools, together with High Performance Reconfigurable Computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of CNN-based applications. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, is analyzed. A sequential CNN architecture, suitable for FPGA implementation, proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results for a typical edge detection algorithm shown that, with a minimum development time, a 10x acceleration, when compared to the software emulation, can be obtained.

Keywords

Parallel Architecture Cellular Neural Network Image Processing Algorithm Communicate Sequential Process FPGA Board 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Rodriguez-Vazquez, A., Linan-Cembrano, G., Carranza, L., Roca-Moreno, E., Carmona-Galan, R., Jimenez-Garrido, F., Dominguez-Castro, R., EMeana, S.: ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs. IEEE Transactions on Circuits and Systems I 51(5), 851–863 (2004)CrossRefGoogle Scholar
  2. 2.
    Nagy, Z., Szolgay, P.: Configurable multilayer CNN-UM emulator on FPGA. IEEE Trans. on Circuits and Systems I 50(6), 774–778 (2003)CrossRefGoogle Scholar
  3. 3.
    Perko, M., Fajfar, I., Tuma, T., Puhan, J.: Low-cost, high-performance CNN simulator implemented in FPGA. In: IEEE Int. Work. on Cellular Neural Networks and Their Applications, CNNA, pp. 277–282 (2000)Google Scholar
  4. 4.
    Malki, S., Spaanenburg, L.: CNN Image Processing on a Xilinx Virtex-II 6000. In: Proceedings ECCTD 2003 (Krakow), pp. 261–264 (2003)Google Scholar
  5. 5.
    Martínez, J.J., Garrigós, F.J., Toledo, F.J., Ferrández, J.M.: High Performance Implementation of an FPGA-Based Sequential DT-CNN. In: Mira, J., Álvarez, J.R. (eds.) IWINAC 2007. LNCS, vol. 4528, pp. 1–9. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  6. 6.
    Densmore, D., Passerone, R.: A Platform-Based Taxonomy for ESL Design. IEEE Design & Test of Computers 23(5), 359–374 (2006)CrossRefGoogle Scholar
  7. 7.
    DRC Computers (2008), http://www.drccomputer.com
  8. 8.
    Impulse Accelerated Technologies Inc.(2003-2009), http://www.impulsec.com
  9. 9.
    Chua, L.O., Yang, L.: Cellular neural networks: theory. IEEE Trans. Circuits and Systems, CAS-35 (1988)Google Scholar
  10. 10.
    Martínez, J.J., Toledo, F.J., Fernández, E., Ferrández, J.M.: A retinomorphic architecture based on discrete-time cellular neural networks using reconfigurable computing. Neurocomputing 71(4-6), 766–775 (2008)CrossRefGoogle Scholar
  11. 11.
    Martínez, J.J., Toledo, F.J., Fernández, E., Ferrández, J.M.: Study of the contrast processing in the early visual system using a neuromorphic retinal architecture. Neurocomputing 72(4-6), 928–935 (2009)CrossRefGoogle Scholar
  12. 12.
    SRC Computers, LLC (2009), http://www.srccomp.com/
  13. 13.
    Silicon Graphics, Inc. (2009), http://www.sgi.com
  14. 14.
    Cray Inc. (2009), http://www.cray.com/
  15. 15.
    Xilinx Inc., Virtex-4 User Guide, data sheet(ug070) (2004), http://www.xilinx.com
  16. 16.
    Court, T.V., Herbordt, M.C.: Families of FPGA-Based Accelerators for Approximate String Matching. ACM Microprocessors & Microsystems 31(2), 135–145 (2007)CrossRefGoogle Scholar
  17. 17.
    Kindratenko, V., Pointer, D.: A case study in porting a production scientific supercomputing application to a reconfigurable computer. In: Proc. IEEE Symposium on Field-Programmable Custom Computing Machines - FCCM 2006, pp. 13–22 (2006)Google Scholar
  18. 18.
    El-Araby, E., El-Ghazawi, T., Le Moigne, J., Gaj, K.: Wavelet Spectral Dimension Reduction of Hyperspectral Imagery on a Reconfigurable Computer. In: IEEE Int. Conference on Field-Programmable Technology (FPT 2004), Brisbane, Australia (December 2004)Google Scholar
  19. 19.
    Michalski, A., Gaj, K., El-Ghazawi, T.: An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers. In: Proc. FPL 2003, pp. 204–219 (2003)Google Scholar
  20. 20.
    Storaasli, O.O.: Scientific Applications on a NASA Reconfigurable Hypercomputer. In: 5th MAPLD Int. Conference, Washington, DC, USA (September 2002)Google Scholar
  21. 21.
    GCC, The GNU Compiler Collection (2009), http://gcc.gnu.org/
  22. 22.

Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • J. Javier Martínez-Álvarez
    • 1
  • F. Javier Garrigós-Guerrero
    • 1
  • F. Javier Toledo-Moreo
    • 1
  • J. Manuel Ferrández-Vicente
    • 1
  1. 1.Dpto. Electrónica, Tecnología de Computadoras y ProyectosUniversidad Politécnica de CartagenaCartagenaSpain

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