Abstract
This paper presents an AES-GCM) core. This core has been designed and implemented taking into account two main aspects: It should provide a real throughput, capable of feeding a Gigabit Ethernet, and should be implemented in a commercial FPGA as part of a System-on-a-Chip (SoC). The AES-GCM encryption/authentication algorithm is of key importance as the fact of being introduced in four different standards, from Ethernet to mass storage devices, suggests. This algorithm is interesting because of two different reasons, first it provides authentication and encryption at the same time, and second its structure is highly parallelized. It is composed of two main blocks: an encryption core (AES in current standards) and a Galois Field multiplier.
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Lázaro, J., Astarloa, A., Bidarte, U., Jiménez, J., Zuloaga, A. (2009). AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_34
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DOI: https://doi.org/10.1007/978-3-642-00641-8_34
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