Abstract
In this paper, we present an implementation of a turbo product codes (TPC) decoder achieved on a novel Reconfigurable Multimedia Accelerator (RMA). The RMA is based on the principle of hierarchical shared memory storage managed through a dedicated local controller favoring high data throughput, while squeezing round-trip memory latencies. The mapping methodology facilitates the characterization of the RMA for a TPC decoder in terms of the communication and computation resources.
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© 2009 Springer-Verlag Berlin Heidelberg
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Yazdani, S., Goubier, T., Pottier, B., Dezan, C. (2009). Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_30
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DOI: https://doi.org/10.1007/978-3-642-00641-8_30
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00640-1
Online ISBN: 978-3-642-00641-8
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