Abstract
In order to meet demanding challenges of increasing computational requirements and stringent power constraints, there is a gradual trend towards heterogeneous multi-processor system-on-chip (MPSoC) designs integrating application specific acceleration engines. One major problem faced by the design tools for mapping of algorithms onto MPSoC architectures is the dimensioning of system components through performance analysis. In this paper, we propose a fast and accurate methodology for rate matching of statically scheduled acceleration engines using modular performance analysis. Given a set of Pareto-optimal hardware accelerator designs and an input workload behavior, the proposed methodology determines cost efficient hardware accelerators that can handle the workload. A motion JPEG case study illustrates the benefit of coupling high level synthesis tools with performance analysis.
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Dutta, H., Hannig, F., Teich, J. (2009). Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. In: Berekovic, M., Müller-Schloer, C., Hochberger, C., Wong, S. (eds) Architecture of Computing Systems – ARCS 2009. ARCS 2009. Lecture Notes in Computer Science, vol 5455. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00454-4_23
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DOI: https://doi.org/10.1007/978-3-642-00454-4_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00453-7
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