Abstract
Due to coupling between lines, the delay in a bus depends on the type of transition causing the delay. For a given sequence of data there is a delay distribution that depends on the sequence characteristics (correlation between consecutive data). This information opens the possibility to reduce the clock cycle for a system with error correcting schemes that handles the slower cases. The large number of transitions needed to calculate a realistic bus delay distribution make the use of electrical simulation impractical for obtaining the delay distribution. This paper presents calculations of the delay distribution for representative cases of sequences, using a computationally efficient method based on a reduced number of electrical simulations. It is shown that for quasi consecutive sequences, the most probable delay is considerably lower than worst case delay.
The authors gratefully acknowledge the collaboration of Isaac Hidalgo in the preliminary simulations for this paper. This research work has been partially supported by the FUTURIC project of the Spanish Ministry of Science and Education, TEC2005/02739.
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Moll, F., Figueras, J., Rubio, A. (2009). Data Dependence of Delay Distribution for a Planar Bus. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_41
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DOI: https://doi.org/10.1007/978-3-540-95948-9_41
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