Abstract
This paper presents an extended high-level model for logic power estimation of multipliers and adders implemented in FPGAs in the presence of glitching and correlation. The model is based on an analytical computation of the switching activity produced in the component and the FPGA implementation details of the component structure. It is extended to consider operands of different word-lengths, both zero-mean and non-zero mean signals, and the glitching produced inside the component, taking into account the sign nature of the autocorrelation coefficients of the components’ inputs. The number of simulations needed for the model characterization is extremely small and can be reduced to only two. As the final power model is analytical, it is capable of providing power estimates in miliseconds. The results show that the mean relative error is within 10% of low-level power estimates given by the XPower tool.
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Jevtic, R., Carreras, C. (2009). Analytical High-Level Power Model for LUT-Based Components. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_37
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DOI: https://doi.org/10.1007/978-3-540-95948-9_37
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
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