Abstract
In this paper, the architecture of a novel reconfigurable array, optimized for high-throughput and low-power Digital Signal Processing, is described. The proposed reconfigurable system consists of 2D array of homogeneous coarse-grain reconfigurable cells organized into a hierarchical two-level architecture. The system has been characterized for performing different DSP tasks. Comparison results demonstrate speedups up to 8X with energy efficiency improvement up to 58% over a state of the art FPGA.
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Lanuzza, M., Perri, S., Corsonello, P., Margala, M. (2009). Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_30
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DOI: https://doi.org/10.1007/978-3-540-95948-9_30
Publisher Name: Springer, Berlin, Heidelberg
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