Abstract
This paper presents a detailed study of the gate driving losses on a multi-mode Step-Down (Buck) DC-DC converter. These gate driving losses are compared to the conduction resistive losses in order to find the optimum gate driving voltage that maximizes the converter’s efficiency. It is shown that gate voltage scaling control can be simplified to a unique step while still achieving efficiencies over 90% at output currents as low as 10mA. Simulation results of a 600mA, 2MHz Step-Down commercial converter, implemented in a 65nm technology, are shown validating the developed models and proposed control methodology.
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Dias, N., Santos, M., Lima, F., Borges, B., Paisana, J. (2009). Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_26
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DOI: https://doi.org/10.1007/978-3-540-95948-9_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
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