Abstract
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. In this paper, we present a performance-driven multilevel framework for the X-based full-chip router. To fully consider performance-driven routing and take advantage of the X-architecture, we apply a novel multilevel routing framework, which adopts a four-stage technique of a trial routing stage, followed by a top-down uncoarsening stage, with an intermediate track routing stage, and then followed by a bottom-up coarsening stage. Compared with the state-of-the-art work, we achieve 100% routing completion for all circuits while reduced the net delay.
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Ho, TY. (2009). A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_21
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DOI: https://doi.org/10.1007/978-3-540-95948-9_21
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
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