Abstract
This paper evaluates the clock generation quality of different digital circuits associated with clock generation and distribution. Circuit’s noise response, jitter, and uncertainty are evaluated for different noise sources and loading conditions. We present performance simulations for inverters and inverter chains implemented in different technologies from AMS and UMC foundries. We show that the device size-scaling trend is increasing the uncertainty associated with this circuits, decreasing their precision. The correlation between circuit’s parameters and selected performance metrics is also highlighted.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
McNeill, J.: Jitter in Ring Oscillators, Ph.D Thesis, Boston University, Boston (1994)
Weigandt, T.C.: Low-Phase-Noise, Low-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers. Ph.D. Thesis, Berkeley (1998)
Hajimiri, A., Limotyrakis, S., Lee, T.H.: Jitter and phase noise in ring oscillators. IEEE J. Solid-State Circuits 34, 790–804 (1999)
Heydari, P.: Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise. IEEE Trans. on Circuits and Systems I. 51, 2404–2416 (2004)
Mesgarzadeh, B., Hansson, M., Alvandpour, A.: Jitter Characteristic in Resonant Clock Distribution. In: 32nd European Solid-State Circuits Conf., pp. 464–467 (2006)
Abidi, A.A., Meyer, R.G.: Noise in Relaxation Oscillators. IEEE Journal of Solid State Circuits 18, 794–802 (1995)
Sakurai, T., Newton, R.: Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid State Circuits 25, 584–594 (1999)
van der Ziel, A.: Thermal Noise in Field-Effect Transistors. Proceedings of the IRE 50(8), 1808–1812 (1962)
Figueiredo, M., Aguiar, R.L.: Predicting Noise and Jitter in CMOS Inverters. In: 3rd Conf. on Ph.D. Research in Microelectronics and Electronics, pp. 21–24 (2007)
Figueiredo, M., Aguiar, R.L.: Noise and Jitter in CMOS Digitally controlled Delay Lines. In: 33th Int. Conf. on Electronics, Circuits and Systems, pp. 1356–1359 (2006)
Bolcato, P., Poujois, R.: A New approach for noise simulation in transient analysis. In: International Symposium on Circuits and Systems, pp. 887–890 (1992)
Chen, L.H., Marek-Sadowska, M., Brewer, F.: Buffer Delay Change in the Presence of Power and Ground Noise. IEEE Trans. on VLSI. 11, 461–473 (2003)
Méndez, M.A., Rubio, A., González, J.L.: An Approach to the Statistical Characterization of the Switching Noise. In: XVIII Conference on Design of Circuits and Integrated Systems. pp. 57–62 (2003)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Figueiredo, M., Aguiar, R.L. (2009). A Study on CMOS Time Uncertainty with Technology Scaling. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_15
Download citation
DOI: https://doi.org/10.1007/978-3-540-95948-9_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
eBook Packages: Computer ScienceComputer Science (R0)