Abstract
This paper presents the performance characteristics of the Intel®Itanium®2-based Montecito processor and compares its performance to the previous generation Madison processor. Measurements on both are done using the industry-standard SPEC CPU2006 benchmarks. The benchmarks were compiled using the Intel Fortran/C++ optimizing compiler and run using the reference data sets. We analyze a large set of processor parameters such as cache misses, TLB misses, branch prediction, bus transactions, resource and data stalls and instruction frequencies. Montecito achieves 1.14× and 1.16× higher (geometric mean) IPC on integer and floating-point applications. We believe that the results and analysis presented in this paper can potentially guide future IA-64 compiler and architectural research.
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References
Naffziger, S., Stackhouse, B., Grutkowski, T., Josephson, D., Desai, J., Alon, E., Horowitz, M.: The implementation of a 2-core multi-threaded itaniumR -family processor. IEEE Journal of Solid-State Circuits 41(1), 197–209 (2006)
McNairy, C., Bhatia, R.: Montecito: A dual-core, dual-thread Itanium processor. IEEE Micro. 25(2), 10–20 (2005)
SPEC CPU (2006), http://www.spec.org/cpu2006
Caliper, http://ieeexplore.ieee.org/iel5/4434/19364/00895108.pdf
Kandiraju, G.B., Sivasubramaniam, A.: Characterizing the d-TLB behavior of SPEC CPU 2000 benchmarks. In: Proceedings of the 2002 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, Marina Del Rey, CA, pp. 129–139 (2002)
Dual-Core Update to the IntelRItaniumR2 Processor Reference Manual, Revision 0.9 (January 2006), http://download.intel.com/design/Itanium2/manuals/30806501.pdf
Cvetanovic, Z., Bhandarkar, D.: Performance characterization of the Alpha 21164 microprocessor using TP and SPEC workloads. In: Proceedings of the 2nd International Symposium on High-Performance Computer Architecture, San Jose, CA, pp. 270–280 (February 1996)
Yeh, T.-Y., Patt, Y.N.: Alternative implementations of two-level adaptive branch prediction. In: Proceedings of the 19th International Symposium on Computer Architecture, Queensland, Australia, pp. 124–134 (1992)
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© 2009 Springer-Verlag Berlin Heidelberg
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Desai, D. et al. (2009). Performance Characterization of Itanium® 2-Based Montecito Processor. In: Kaeli, D., Sachs, K. (eds) Computer Performance Evaluation and Benchmarking. SBW 2009. Lecture Notes in Computer Science, vol 5419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-93799-9_3
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DOI: https://doi.org/10.1007/978-3-540-93799-9_3
Publisher Name: Springer, Berlin, Heidelberg
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