Abstract
This paper presents a novel hardware architecture for genetic vector quantizer (VQ) design. The architecture is based on steady-state genetic algorithm (GA). It adopts a novel architecture based on shift registers for accelerating mutation and crossover operations while reducing area cost. It also uses a pipeline architecture for fitness evaluation. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for VQ optimization attaining both high performance and low computational time.
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Lin, TK., Li, HY., Hwang, WJ., Ou, CM., Weng, SK. (2008). Genetic Vector Quantizer Design on Reconfigurable Hardware. In: Li, X., et al. Simulated Evolution and Learning. SEAL 2008. Lecture Notes in Computer Science, vol 5361. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-89694-4_48
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DOI: https://doi.org/10.1007/978-3-540-89694-4_48
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-89693-7
Online ISBN: 978-3-540-89694-4
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