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Genetic Vector Quantizer Design on Reconfigurable Hardware

  • Ting-Kuan Lin
  • Hui-Ya Li
  • Wen-Jyi Hwang
  • Chien-Min Ou
  • Sheng-Kai Weng
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5361)

Abstract

This paper presents a novel hardware architecture for genetic vector quantizer (VQ) design. The architecture is based on steady-state genetic algorithm (GA). It adopts a novel architecture based on shift registers for accelerating mutation and crossover operations while reducing area cost. It also uses a pipeline architecture for fitness evaluation. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for VQ optimization attaining both high performance and low computational time.

Keywords

Shift Register Direct Memory Access Parent String Average Distortion Memory Access Time 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Ting-Kuan Lin
    • 1
  • Hui-Ya Li
    • 1
  • Wen-Jyi Hwang
    • 1
  • Chien-Min Ou
    • 2
  • Sheng-Kai Weng
    • 1
  1. 1.Department of Computer Science and Information EngineeringNational Taiwan Normal UniversityTaipeiTaiwan
  2. 2.Department of Electronics EngineeringChing-Yun UniversityChungliTaiwan

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