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A Dynamic Assertion-Based Verification Platform for Validation of UML Designs

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Book cover Automated Technology for Verification and Analysis (ATVA 2008)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 5311))

Abstract

For quite some time, the Unified Modeling Language (UML) [5] has been adopted by designers of safety critical control systems such as automotive and aviation control. This has led to an increased emphasis on setting up a validation flow over UML that can be used to guarantee the correctness of UML models. In this paper, we present a dynamic property verification (DPV) framework for validation of UML designs. The verification engine is built on top of Rhapsody [3], a popular UML simulator, using the concept of dynamic property monitoring over simulation runs. In view of the growing popularity of model-based development, we believe that the verification methodology presented in this paper is of immediate practical value to the UML-based design community.

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References

  1. Bhaduri, P., Ramesh, S.: Model Checking of Statechart Models: Survey and Recent Directions (2004)

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  2. Dasgupta, P.: A Roadmap for Formal Property Verification. Springer, Heidelberg (2006)

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  3. Harel, D., Kugler, H.: The Rhapsody semantics of Statecharts (or, On the Executable Core of the UML). In: Ehrig, H., Damm, W., Desel, J., Große-Rhode, M., Reif, W., Schnieder, E., Westkämper, E. (eds.) INT 2004. LNCS, vol. 3147, pp. 325–354. Springer, Heidelberg (2004)

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  4. http://www.lin-subbus.org/

  5. Object Management Group, Unified Modeling Language Specification, Version 1.4, Draft, OMG(2001), http://cgi.omg.org/cgibin/docad/018214

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Author information

Authors and Affiliations

  1. Indian Institute of Technology Kharagpur, India

    Ansuman Banerjee, Sayak Ray, Pallab Dasgupta & Partha Pratim Chakrabarti

  2. General Motors India Science Labs, India

    S. Ramesh & P. Vignesh V. Ganesan

Authors
  1. Ansuman Banerjee
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  2. Sayak Ray
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  3. Pallab Dasgupta
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  4. Partha Pratim Chakrabarti
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  5. S. Ramesh
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  6. P. Vignesh V. Ganesan
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Editor information

Editors and Affiliations

  1. College of Information & Communication, Division of Computer and Communication Engineering, Korea University, Anam-Dong, Seongbuk-Gu, 136-701, Seoul, South Korea

    Sungdeok (Steve) Cha

  2. Departmnet of Computer Science and Engineering, Korea University, Anam-Dong, Seongbuk-Gu, 136-702, Seoul, South Korea

    Jin-Young Choi

  3. KAIST, Department of Computer Science, Guseong-Dong, Yuseong-Gu, 305-701, Daejon, South Korea

    Moonzoo Kim

  4. School of Engineering and Applied Science, Department of Computer and Information Science,, University of Pennsylvania, Levine Hall, Room 602, 3330 Walnut Street, PA 19104-6389, Philadelphia, USA

    Insup Lee

  5. Thomas M. Siebel Center , University of Illinois at Urbana-Champaign, 201 N. Goodwin Avenue, IL 61801-2302, Urbana, USA

    Mahesh Viswanathan

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© 2008 Springer-Verlag Berlin Heidelberg

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Banerjee, A., Ray, S., Dasgupta, P., Chakrabarti, P.P., Ramesh, S., Ganesan, P.V.V. (2008). A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. In: Cha, S.(., Choi, JY., Kim, M., Lee, I., Viswanathan, M. (eds) Automated Technology for Verification and Analysis. ATVA 2008. Lecture Notes in Computer Science, vol 5311. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-88387-6_18

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  • DOI: https://doi.org/10.1007/978-3-540-88387-6_18

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-88386-9

  • Online ISBN: 978-3-540-88387-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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