Abstract
This paper presents a framework for building and modeling a new-generation self-adaptive systems. The first part of the paper proposes an architecture of a self-adaptive networked entity that forms the basic element of the approach. The second part describes a modeling environment based on Matlab / Simulink and one possible implementation of the self-adaptive networked entity. A physical realization of the proposed system is demonstrated on the computation of a simple FIR filter in several FPGAs acting as hardware in the loop in Matlab / Simulink.
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References
Krikke, J.: T-engine: Japans ubiquitous computing architecture is ready for prime time. IEEE Pervasive Computing 4(2), 4–9 (2005)
The AETHER project web page - The AETHER consorcium (2006), http://www.aether-ist.org.The
Paulsson, K., Hübner, M., Becker, J., Philippe, J.-M., Gamrat, C.: On-line routing of reconfigurable functions for future self-adaptive systems - investigations within the AETHER project. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2007) (2007)
Worm, F., Ienne, P., Thiran, P., De Micheli, G.: An adaptive low-power transmission scheme for on-chip networks. In: Proceedings of the ACM International Symposium on System Synthesis (ISSS 2002) (2002)
Li, L., Vijaykrishnan, N., Kandemir, M., Irwin, M.J.: Adaptive error protection for energy efficiency. In: Proceedings of the International Conference on Computer Aided Design (ICCAD 2003) (2003)
Kahle, J.A., Day, M.N., Hofstee, H.P., Johns, C.R., Maeurer, T.R., Shippy, D.: Introduction to the Cell multiprocessor. IBM J. Res. Dev. 49(4/5), 589–604 (2005)
Millberg, M., Nilsson, E., Thid, R., Jantsch, A.: Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip (2004), citeseer.ist.psu.edu/millberg04guaranteed.html
Guerrier, P., Greiner, A.: A generic architecture for on-chip packet switched interconnections (2000), citeseer.ist.psu.edu/guerrier00generic.html
The RECONF2 project web page. The RECONF2 consortium (2002), http://reconf.org
Bartosinski, R., DanÄ›k, M., HonzÃk, P., MatouÅ¡ek, R.: Dynamic reconfiguration in FPGA-based SoC designs. In: J.S., et al. (eds.) Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop DDECS 2005, pp. 129–136. University of West Hungary (2005)
Horta, E.L., Lockwood, J.W., Parlour, D.: Dynamic hardware plugins in an FPGA with partial runtime reconfiguration. In: Ackland, B. (ed.) Proceedings of the 39th Design Automation Conference, pp. 343–348. ACM Press, New York (2002)
Kielblik, R., Moreno, J.M., Napieralski, A., Jablonski, G., Szymanski, T.: High-level partitioning of digital systems based on dynamically reconfigurable devices. In: Glesner, M., Zipf, P., Renovell, M. (eds.) Proceedings of the 12th International Conference on Field-Programmable Logic and Applications, pp. 271–280. Springer, Heidelberg (2002)
Wirthlin, M.J., Hutchings, B.L.: Improving functional density using run-time circuit reconfiguration. IEEE Trans. VLSI Syst. 6(2), 247–256 (2002)
Robertson, I., Irvine, J., Lysaght, P., Robinson, D.: Timing verification of dynamically reconfigurable logic for the Xilinx Virtex FPGA series. In: Schlag, M., Trimberger, S. (eds.) Proceedings of the 10th International Symposium on Field-Programmable Gate Arrays, pp. 127–132. ACM Press, New York (2002)
Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C.-C., III, J.F.B., Agarwal, A.: On-chip interconnection architecture of the Tile processor. IEEE Micro. 27(5), 15–31 (2007)
C. I. of Electrical and I. S. Electronics Engineers. In: IEEE Standard for Scalable Coherent Interface. IEEE Std., pp. 1596–1992. IEEE Standards Office, New York (1993)
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Danek, M., Philippe, JM., Honzik, P., Gamrat, C., Bartosinski, R. (2008). Self-Adaptive Networked Entities for Building Pervasive Computing Architectures. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds) Evolvable Systems: From Biology to Hardware. ICES 2008. Lecture Notes in Computer Science, vol 5216. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85857-7_9
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DOI: https://doi.org/10.1007/978-3-540-85857-7_9
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