Abstract
For the memory intensive task of graph reduction, modern PCs are limited not by processor speed, but by the rate that data can travel between processor and memory. This limitation is known as the von Neumann bottleneck. We explore the effect of widening this bottleneck using a special-purpose graph reduction machine with wide, parallel memories. Our prototype machine – the Reduceron – is implemented using an FPGA, and is based on a simple template-instantiation evaluator. Running at only 91.5MHz on an FPGA, the Reduceron is faster than mature bytecode implementations of Haskell running on a 2.8GHz PC.
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Naylor, M., Runciman, C. (2008). The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA. In: Chitil, O., Horváth, Z., Zsók, V. (eds) Implementation and Application of Functional Languages. IFL 2007. Lecture Notes in Computer Science, vol 5083. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85373-2_8
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DOI: https://doi.org/10.1007/978-3-540-85373-2_8
Publisher Name: Springer, Berlin, Heidelberg
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