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Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking

  • J. Barnat
  • L. Brim
  • P. Šimeček
  • M. Weber
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4963)

Abstract

Revisiting resistant graph algorithms are those, whose correctness is not vulnerable to repeated edge exploration. Revisiting resistant I/O efficient graph algorithms exhibit considerable speed-up in practice in comparison to non-revisiting resistant algorithms. In the paper we present a new revisiting resistant I/O efficient LTL model checking algorithm. We analyze its theoretical I/O complexity and we experimentally compare its performance to already existing I/O efficient LTL model checking algorithms.

Keywords

Main Memory External Memory Internal Memory Cycle Detection Single Source Short Path 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • J. Barnat
    • 1
  • L. Brim
    • 1
  • P. Šimeček
    • 1
  • M. Weber
    • 2
  1. 1.Masaryk University BrnoCzech Republic
  2. 2.University of TwenteThe Netherlands

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