Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices

  • Thomas Marconi
  • Yi Lu
  • Koen Bertels
  • Georgi Gaydadjiev
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)


In this paper, we propose an online hardware task scheduling and placement algorithm and evaluate it performance. Experimental results on large random task set show that our algorithm outperforms the existing algorithms in terms of reduced total wasted area up to 89.7%, has 1.5 % shorter schedule time and 31.3% faster response time.


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  1. 1.
    Lysaght, P., Dunlop, J.: Dynamic Reconfiguration of FPGAs. In: More FPGAs, pp. 82–94, EE&CS Books, Abingdon (1993)Google Scholar
  2. 2.
    Eldredge, J.G., Hutchings, B.L.: Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration. In: Proceeding of IEEE workshop on FPGAs for custom computing machines, pp. 180–188 (1994)Google Scholar
  3. 3.
    Villasenor, J., Jones, C., Schoner, B.: Video Communications Using Rapidly Reconfigurable Hardware. IEEE Transactions on circuits and systems for video technology 5(6), 565–567 (1995)CrossRefGoogle Scholar
  4. 4.
    Vuillemin, J., Bertin, P., Roncin, D., Shand, M., Touati, H., Boucard, P.: Programmable Active Memories: Reconfigurable Systems Come of Age. IEEE Transactions on VLSI Systems 4(1), 56–69 (1996)CrossRefGoogle Scholar
  5. 5.
    Eggers, H., Lysaght, P., Dick, H., McGregor, G.: Fast Reconfigurable Crossbar Switching in FPGAs. In: Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, pp. 297–306 (1996)Google Scholar
  6. 6.
    Wirthlin, M.J., Hutchings, B.L.: Sequencing Run-Time Reconfigured Hardware with Software. In: ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 122–128 (1996)Google Scholar
  7. 7.
    Steiger, C., Walder, H., Platzner, M.: Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Cheung, P.Y.K., Constantinides, G.A., de Sousa, J.T. (eds.) FPL 2003. LNCS, vol. 2778, pp. 575–584. Springer, Heidelberg (2003)Google Scholar
  8. 8.
    Steiger, C., Walder, H., Platzner, M.: Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks. IEEE transaction on Computers 53(11), 1393–1407 (2004)CrossRefGoogle Scholar
  9. 9.
    Chen, Y., Hsiung, P.: Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds.) EUC 2005. LNCS, vol. 3824, pp. 489–498. Springer, Heidelberg (2005)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Thomas Marconi
    • 1
  • Yi Lu
    • 1
  • Koen Bertels
    • 1
  • Georgi Gaydadjiev
    • 1
  1. 1.Computer Engineering LaboratoryEEMCS, TU DelftThe Netherlands

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