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Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study

  • Steffen Köhler
  • Jan Schirok
  • Jens Braunes
  • Rainer G. Spallek
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)

Abstract

In this paper, we examine the efficiency of the ARRIVE architecture, a coarse-grain reconfigurable datapath extension to an embedded RISC microprocessor. It is considered platform specific, optimized for the media and communication processing domain. Detailed chip area requirements are obtained through the mapping to an UMC 0.18μm standard cell ASIC process layout. Furthermore, we present hardware utilization and power simulation results of six media/communication benchmark applications based on post-layout process information. As a result, we can recognize increased area efficiency (\(\frac{operations}{mm^2\cdot s}\)) and power efficiency (\(\frac{operations}{mW\cdot s}\)) of the reconfigurable datapath extended RISC microprocessor.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Steffen Köhler
    • 1
  • Jan Schirok
    • 1
  • Jens Braunes
    • 1
  • Rainer G. Spallek
    • 1
  1. 1.Institute of Computer EngineeringTechnische Universität DresdenDresdenGermany

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