Abstract
In this paper, we examine the efficiency of the ARRIVE architecture, a coarse-grain reconfigurable datapath extension to an embedded RISC microprocessor. It is considered platform specific, optimized for the media and communication processing domain. Detailed chip area requirements are obtained through the mapping to an UMC 0.18μm standard cell ASIC process layout. Furthermore, we present hardware utilization and power simulation results of six media/communication benchmark applications based on post-layout process information. As a result, we can recognize increased area efficiency (\(\frac{operations}{mm^2\cdot s}\)) and power efficiency (\(\frac{operations}{mW\cdot s}\)) of the reconfigurable datapath extended RISC microprocessor.
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Köhler, S., Schirok, J., Braunes, J., Spallek, R.G. (2008). Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_32
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DOI: https://doi.org/10.1007/978-3-540-78610-8_32
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-78609-2
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