PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications

  • Frank Hannig
  • Holger Ruckdeschel
  • Hritam Dutta
  • Jürgen Teich
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)


In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks.


Iteration Point Processor Array Loop Body Hardware Accelerator Processor Element 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Frank Hannig
    • 1
  • Holger Ruckdeschel
    • 1
  • Hritam Dutta
    • 1
  • Jürgen Teich
    • 1
  1. 1.Hardware/Software Co-Design, Department of Computer ScienceUniversity of Erlangen-NurembergGermany

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