Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs
This paper presents implementation of the double precision exponential function. A novel table-based architecture, together with short Taylor expansion, provides low latency (30 clock cycles) which is comparable to 32-bit implementations. Low area consumption of a single exp() module (roughtly 4% of XC4LX200) allows implementation of several parallel modules on a single FPGAs. The exp() function was implemented on the SGI RASC platform, thus external memory interface limitation allowed only a twin module parallelism. Each module is capable of processing at speed of 200 MHz with max. error of 1 ulp, RMSE equals 0,62. This implementation aims primarily to meet quantum chemistry’s huge and strict requirements of precision and speed.
KeywordsHPRC (High Performance Reconfigurable Computing) FPGA elementary function exponent function
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