Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard

  • Vítor Silva
  • Rui Duarte
  • Mário Véstias
  • Horácio Neto
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)


This paper describes the design and implementation of a unit to calculate the significand of a double precision floating point divider according to the IEEE-754 standard. Instead of the usual digit recurrence techniques, such as SRT-2 and SRT-4, it uses an iterative technique based on the Goldsmith algorithm. As multiplication is the main operation of this algorithm, its implementation is able to take advantage of the efficiency of the embedded multipliers available in the FPGAs. The results obtained indicate that the multiplier-based iterative algorithms can achieve better performance than the alternative digit recurrence algorithms, at the cost of some area overhead.


Word Length Polynomial Approximation LookUp Table Double Precision Area Overhead 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Vítor Silva
    • 1
  • Rui Duarte
    • 1
  • Mário Véstias
    • 2
  • Horácio Neto
    • 1
  1. 1.INESC-ID/IST/UTLTechnical University of LisbonPortugal
  2. 2.INESC-ID/ISEL/IPLPolytechnic Institute of LisbonPortugal

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