An FPGA Run-Time Parameterisable Log-Normal Random Number Generator

  • Pedro Echeverría
  • David B. Thomas
  • Marisa López-Vallejo
  • Wayne Luk
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)


Monte Carlo financial simulation relies on the generation of random variables with different probability distribution functions. These simulations, particularly the random number generator (RNG) cores, are computationally intensive and are ideal candidates for hardware acceleration. In this work we present an FPGA based Log-normal RNG ideally suited for financial Monte Carlo simulations, as it is run-time parameterisable and compatible with variance reduction techniques. Our architecture achieves a throughput of one sample per cycle with a 227.6 MHz clock on a Xilinx Virtex-4 FPGA.


Pipeline Stage Input Range Single Precision Point Arithmetic Pipeline Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Black, F., Scholes, M.: The pricing of options and corporate liabilities. The Journal of Political Economy 81(3), 637–654 (1973)CrossRefGoogle Scholar
  2. 2.
    Merton, R.C.: Theory of rational option pricing. The Bell Journal of Economics and Management Science 4(1), 141–183 (1973)CrossRefMathSciNetGoogle Scholar
  3. 3.
    Gentle, J.E.: Random Number Generation and Monte Carlo Methods. Springer, Heidelberg (1998)zbMATHGoogle Scholar
  4. 4.
    Bratley, P., Fox, B.L., Schrage, L.E.: A Guide to Simulation. Springer, Heidelberg (1983)zbMATHGoogle Scholar
  5. 5.
    Zhang, G.L., et al.: Reconfigurable acceleration for Monte Carlo based financial simulation. In: Proc. IEEE International Conference on Field-Programmable Technology, pp. 215–222 (2005)Google Scholar
  6. 6.
    Cheung, R.C.C., Lee, D.-U., Luk, W., Villasenor, J.D.: Hardware generation of arbitrary random number distributions from uniform distributions via the inversion method. IEEE Transactions on Very Large Integration (VLSI) Systems 18(8), 952–962 (2007)CrossRefGoogle Scholar
  7. 7.
    Thomas, D.B., Luk, W.: Non-uniform random number generation through piecewise linear approximations. IET Computers and Digital Techniques 1(7), 312–321 (2007)CrossRefGoogle Scholar
  8. 8.
    ——, Efficient hardware generation of random variates with arbitrary distributions, In: Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 57–66 (2006)Google Scholar
  9. 9.
    Echeverría, P., López-Vallejo, M.: FPGA gaussian random number generator based on quintic hermite interpolation inversion. In: IEEE International Midwest Symposium on Circuits and Systems, pp. 871–874 (2007)Google Scholar
  10. 10.
    Govindu, G., Zhou, L., Choi, S., Prasanna, V.: Analysis of high-performance floating-point arithmetic on FPGAs. In: IEEE International Parallel and Distributed Processing Symposium, pp. 26–30 (2004)Google Scholar
  11. 11.
    Doss, C.C., Riley, R.L.: FPGA-Based implementation of a robust IEEE-754 exponential unit. In: IEEE Field-Programmable Custom Computing Machines, pp. 229–238 (2004)Google Scholar
  12. 12.
    Detrey, J., de Dinechin, F.: A parameterized floating-point exponential function for FPGAs. In: IEEE International Conference Field-Programmable Technology, pp. 27–34 (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Pedro Echeverría
    • 1
  • David B. Thomas
    • 2
  • Marisa López-Vallejo
    • 1
  • Wayne Luk
    • 2
  1. 1.Dept. de Ingeniería ElectrónicaUniversidad Politécnica de Madrid(Spain)
  2. 2.Dept. of ComputingImperial College London(United Kingdom)

Personalised recommendations