Skip to main content
SpringerLink
Log in

The Instruction-Set Extension Problem: A Survey

  • Conference paper
Reconfigurable Computing: Architectures, Tools and Applications (ARC 2008)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4943))

Included in the following conference series:

Abstract

Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction-set, which can be tuned towards specific requirements. The identification, definition and implementation of those operations that provide the largest performance improvement and that should be hardwired, extending in this way the Instruction-Set, constitutes a major challenge. The purpose of this paper is to investigate and study the issues regarding the customization of an Instruction-Set in function of the specific requirements of an application. Additionally, the paper provides an overview of all relevant aspects of the problem and compensates the lack of a general view of the problem in the existing literature.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Keutzer,: From ASIC to ASIP: The next design discontinuity. In: ICCD 2002 (2002)

    Google Scholar 

  2. Holmer: Automatic design of computer instruction sets. PhD thesis (1993)

    Google Scholar 

  3. Huang: Generating instruction sets and microarchitectures from applications. In: ICCAD 1994, (1994)

    Google Scholar 

  4. Huang: Synthesis of instruction sets for pipelined microprocessors. In: DAC 1994, (1994)

    Google Scholar 

  5. Van Praet: Instruction set definition and instruction selection for ASIPs. In: ISSS 1994, (1994)

    Google Scholar 

  6. Liem: Instruction-set matching and selection for DSP and ASIP code generation. In: ED & TC 1994, (1994)

    Google Scholar 

  7. Choi,: Synthesis of application specific instructions for embedded DSP software. IEEE Trans. on Comp. 48(6), 603–614 (1999)

    Article  Google Scholar 

  8. Faraboschi,: LX: a technology platform for customizable VLIW embedded processing. ACM SIGARCH Computer Architecture News, Special Issue. In: Proceedings of the 27th annual international symposium on Computer architecture (ISCA 2000) 28(2), 203–213 (2003)

    Article  Google Scholar 

  9. Wang: Hardware/software instruction set configurability for System-on-Chip processors. In: DAC 2001 (2001)

    Google Scholar 

  10. Arnold: Designing domain-specific processors. In: CODES 2001(2001)

    Google Scholar 

  11. Kastner,: Instruction generation for hybrid reconfigurable systems. ACM TODAES 7(4), 605–627 (2002)

    Article  Google Scholar 

  12. Atasu: Automatic application-specific instruction-set extensions under microarchitectural constraints. In: DAC 2003 (2003)

    Google Scholar 

  13. Atasu: An integer linear programming approach for identifying instruction-set extensions. In: CODES+ISSS 2005 (2005)

    Google Scholar 

  14. Galuzzi: Automatic selection of application-specific instruction-set extensions. In: CODES+ISSS 2006 (2006)

    Google Scholar 

  15. Alomary: A hardware/software codesign partitioner for ASIP design. In: ICECS 1996 (1996)

    Google Scholar 

  16. Athanas,: Processor reconfiguration through instruction-set metamorphosis. IEEE Computer 26(3), 11–18 (1993)

    Google Scholar 

  17. Razdan: PRISC software acceleration techniques. In: ICCS 1994 (1994)

    Google Scholar 

  18. Wirthlin: DISC: The dynamic instruction set computer. In: FPGAs for Fast Board Devel. and Reconf. Comp. vol. 2607, pp. 92–103 (1995)

    Google Scholar 

  19. Geurts: Synthesis of Accelerator Data Paths for High-Throughput Signal Processing Applications. PhD thesis (1995)

    Google Scholar 

  20. Geurts,: Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications. Kluwer Academic Publishers, Norwell (1997)

    MATH  Google Scholar 

  21. Hauser: GARP: a mips processor with a reconfigurable coprocessor. In: FCCM 1997 (1997)

    Google Scholar 

  22. Niemann: Hardware/software partitioning using integer programming. In: EDTC 1996 (1996)

    Google Scholar 

  23. Niemann,: An algorithm for hardware/software partitioning using mixed integer linear programming. ACM TODAES, Special Issue: Partitioning Methods for Embedded Systems 2(2), 165–193 (1997)

    Google Scholar 

  24. De Micheli,: Hardware/software co-design. Proc. of IEEE 85(3), 349–365 (1997)

    Article  Google Scholar 

  25. Baleani, Sangiovanni-Vincentelli, A.: HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. In: CODES 2002 (2002)

    Google Scholar 

  26. Arató: Hardware-software partitioning in embedded system design. In: WISP 2003 (2003)

    Google Scholar 

  27. Gschwind: Instruction set selection for ASIP design. In: CCODES 1999 (1999)

    Google Scholar 

  28. Pozzi: Automatic topology-based identification of instruction-set extensions for embedded processors. Technical Report CS 01/377, EPFL, DI-LAP, Lausanne (December 2001)

    Google Scholar 

  29. Clark: Automatically generating custom instruction set extensions. In: WASP 2002 (2002)

    Google Scholar 

  30. Peymandoust: Automatic instruction set extension and utilization for embedded processors. In: ASAP (2003)

    Google Scholar 

  31. Clark,: Processor acceleration through automated instruction set customization. In: MICRO 36

    Google Scholar 

  32. Cong: Application-specific instruction generation for configurable processor architectures. In: FPGA 2004 (2004)

    Google Scholar 

  33. Rao, S.: Partitioning by regularity extraction. In: DAC 1992 (1992)

    Google Scholar 

  34. Arnold: Automatic detection of recurring operation patterns. In: CODES 1999 (1999)

    Google Scholar 

  35. Kastner: Instruction generation for hybrid reconfigurable systems. In: ICCAD 2001 (2001)

    Google Scholar 

  36. Fortin: The graph isomorphism problem. Technical Report TR 96-20, Department of Computing Science, University of Alberta, Canada (July 1996)

    Google Scholar 

  37. Chen,: Graph isomorphism and identification matrices: Parallel algorithms. IEEE Trans. on Paral. and Distr. Systems 7(3), 308–319 (1996)

    Article  Google Scholar 

  38. Coudert: New ideas for solving covering problems. In: DAC 1995 (1995)

    Google Scholar 

  39. Coudert: On solving covering problems. In: DAC 1996 (1996)

    Google Scholar 

  40. Brisk: Instruction generation and regularity extraction for reconfigurable processors. In: CASES 2002 (2002)

    Google Scholar 

  41. Yu: Scalable custom instructions identification for instruction-set extensible processors. In: CASES 2004 (2004)

    Google Scholar 

  42. Aletà,: Removing communications in clustered microarchitectures through instruction replication. ACM TACO 1(2), 127–151 (2004)

    Article  Google Scholar 

  43. Vassiliadis, S., Bertels, K., Galuzzi, C.: A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, vol. 4419, pp. 130–141. Springer, Heidelberg (2007)

    Google Scholar 

  44. Galuzzi: A linear complexity algorithm for the generation of multiple input single output instructions of variable size. In: SAMOS VII Works

    Google Scholar 

  45. Liao: Instruction selection using binate covering for code size optimization. In: ICCAD 1995 (1995)

    Google Scholar 

  46. Liao,: A new viewpoint on code generation for directed acyclic graphs. ACM TODAES 3(1), 51–75 (1998)

    Article  Google Scholar 

  47. Rao, S.: On clustering for maximal regularity extraction. IEEE Trans, on CAD 12(8), 1198–1208 (1993)

    Google Scholar 

  48. Rao, S.: Hierarchical design space exploration for a class of digital systems. IEEE Trans. on VLSI Systems 1(3), 282–295 (1993)

    Article  Google Scholar 

  49. Janssen: A specification invariant technique for regularity improvement between flow-graph clusters. In: EDTC 1996 (1996)

    Google Scholar 

  50. Huang: Managing dynamic reconfiguration overhead in system-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. In: DATE 2001 (2001)

    Google Scholar 

  51. Moreano: Datapath merging and interconnection sharing for reconfigurable architectures. In: ISSS 2002 (2002)

    Google Scholar 

  52. Sun: Synthesis of custom processors based on extensible platforms. In: ICCAD 2002 (2002)

    Google Scholar 

  53. Imai: An integer programming approach to instruction implementation method selection problem. In: EURO-DAC 1992 (1992)

    Google Scholar 

  54. Grasselli,: A method for minimizing the number of internal states in incompletely specified sequential networks. IEEE Trans. Electron. Comp. EC-14, 350–359 (1965)

    Article  Google Scholar 

  55. Brayton: Boolean relations and the incomplete specification of logic networks. In: ICCAD 1989 (1989)

    Google Scholar 

  56. Liao: Solving covering problems using LPR-based lower bounds. In: DAC 1997 (1997)

    Google Scholar 

  57. Li: Effective bounding techniques for solving unate and binate covering problems. In: DAC 2005 (2005)

    Google Scholar 

  58. Alippi: A DAG-based design approach for reconfigurable VLIW processors. In: DATE 1999 (1999)

    Google Scholar 

  59. Galuzzi: The spiral search: A linear complexity algorithm for the generation of convex multiple input multiple output instruction-set extensions. In: ICFPT 2007 (2007)

    Google Scholar 

  60. Huynh: An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customizations. In: CASES 2007 (2007)

    Google Scholar 

  61. Yu: Disjoint pattern enumeration for custom instructions identification. In: FPL 2007 (2007)

    Google Scholar 

  62. Bonzini: A retargetable framework for automated discovery of custom instructions. In: ASAP 2007 (2007)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Computer Engineering, EEMCS, Delft University of Technology, The Netherlands

    Carlo Galuzzi & Koen Bertels

Authors
  1. Carlo Galuzzi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Koen Bertels
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Roger Woods Katherine Compton Christos Bouganis Pedro C. Diniz

Rights and permissions

Reprints and permissions

Copyright information

© 2008 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Galuzzi, C., Bertels, K. (2008). The Instruction-Set Extension Problem: A Survey. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_21

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-78610-8_21

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-78609-2

  • Online ISBN: 978-3-540-78610-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation