ARISE Machines: Extending Processors with Hybrid Accelerators

  • Nikolaos Vassiliadis
  • George Theodoridis
  • Spiridon Nikolaidis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)


ARISE introduces a systematic approach to extend once a processor to support thereafter the coupling of an arbitrary number of Custom Computing Units (CCUs). A CCU, hardwired or reconfigurable, can be utilized in a hybrid, tight and/or loose, model of computation. By selecting the appropriate model for each part of the application, the complete application space can be considered for acceleration, resulting to significant performance improvements. To support these features ARISE proposes: i) a machine organization, ii) a set of Instruction Set Extensions (ISEs), and iii) a micro-architecture. To evaluate our proposal, a MIPS processor is extended with the ARISE infrastructure and implemented on an FPGA. Results show that the ARISE infrastructure can easily fit into the timing model of the processor. A set of benchmarks is mapped on the evaluation machine and it is proved that exploiting the hybrid model of computation, performance improvements of up to 68% are achieved compared to the case when only one model is supported. This results to significant application speedups from 2.4x up to 4.8x.


reconfigurable instruction set processor coprocessor custom unit FPGA 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Nikolaos Vassiliadis
    • 1
  • George Theodoridis
    • 1
  • Spiridon Nikolaidis
    • 1
  1. 1.Electronics and Computer Section, Physics DepartmentAristotle University of ThessalonikiGreece

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