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A Parallel Hardware Architecture for Image Feature Detection

  • Vanderlei Bonato
  • Eduardo Marques
  • George A. Constantinides
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)

Abstract

This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for hardware implementation of the SIFT algorithm and proposes specific hardware optimizations considered fundamental to embed whole system on a single chip, which implements in parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.

Keywords

Clock Cycle Scale Invariant Feature Transform Gradient Magnitude CMOS Image Sensor CORDIC Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Vanderlei Bonato
    • 1
  • Eduardo Marques
    • 1
  • George A. Constantinides
    • 2
  1. 1.Institute of Mathematical and Computing SciencesThe University of São PauloSão CarlosBR
  2. 2.Department of Electrical and Electronic EngineeringImperial College LondonLondonUK

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