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Physical Design of FPGA Interconnect to Prevent Information Leakage

  • Sumanta Chaudhuri
  • Sylvain Guilley
  • Philippe Hoogvorst
  • Jean-Luc Danger
  • Taha Beyrouthy
  • Alin Razafindraibe
  • Laurent Fesquet
  • Marc Renaudin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)

Abstract

In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

Keywords

Smart Card Switch Point Register Transfer Level Switch Matrix Differential Power Analysis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Sumanta Chaudhuri
    • 1
  • Sylvain Guilley
    • 1
  • Philippe Hoogvorst
    • 1
  • Jean-Luc Danger
    • 1
  • Taha Beyrouthy
    • 2
  • Alin Razafindraibe
    • 2
  • Laurent Fesquet
    • 2
  • Marc Renaudin
    • 2
  1. 1.GET / Télécom Paris, CNRS – LTCI (UMR 5141)PARIS Cedex 13France
  2. 2.TIMA Laboratory (INPG), CIS group GRENOBLEFrance

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