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A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation

  • Antonio Roldao Lopes
  • George A. Constantinides
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4943)

Abstract

As Field Programmable Gate Arrays (FPGAs) have reached capacities beyond millions of equivalent gates, it becomes possible to accelerate floating-point scientific computing applications. One type of calculation that is commonplace in scientific computation is the solution of systems of linear equations. A method that has proven in software to be very efficient and robust for finding such solutions is the Conjugate Gradient algorithm. In this paper we present a parallel hardware Conjugate Gradient implementation. The implementation is particularly suited for accelerating multiple small to medium sized dense systems of linear equations. Through parallelization it is possible to convert the computation time per iteration for an order n matrix from Θ(n 2) cycles for a software implementation to Θ(n). I/O requirements are scalable and converge to a constant value with the increase of matrix order. Results on a VirtexII-6000 demonstrate sustained performance of 5 GFLOPS and projected results on a Virtex5-330 indicate sustained performance of 35 GFLOPS. The former result is comparable to high-end CPUs, whereas the latter represents a significant speedup.

Keywords

Conjugate Gradient Clock Cycle Conjugate Gradient Method Conjugate Gradient Algorithm Sustained Performance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Antonio Roldao Lopes
    • 1
  • George A. Constantinides
    • 1
  1. 1.Electrical & Electronic EngineeringImperial College LondonLondonEngland

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