Abstract
DIMMnet-2 is a network interface for PC cluster, plugged into a DIMM slot. Connecting network interface into commonly used memory bus reduces the cost of building PC cluster compared with using expensive machines with recent high performance I/O bus like PCIX. Moreover, low latency communication from the host CPU can be achieved. In this paper, implementation of the mechanisms for low latency communication on the DIMMnet-2 prototype board by making the best use of the memory slot is shown. Its latency for 4 Bytes data transfer is only 1.4 μs which is lower than those of InfiniBand and QsNET II on condition those host processes are Intel Xeon.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Boden, N.J., Cohen, D., Felderman, R.E., Kulawik, A.E., Seitz, C.L., Seizovic, J.N., Su, W.-K.: Myrinet - A gigabit per second local area network. IEEE Micro 15(1), 29–36 (1995)
Petrini, F., Fang, W.-c., Hoisie, A., Coll, S., Frachtenberg, E.: The Quadrics Network: High-Performance Clustering Technology. IEEE Micro 22(1), 46–57 (2002)
InfiniBand Trade Association. http://www.infinibandta.org/
Intel 915G/915GV/910GL/915P Express Chipset Datasheet (Sepember 2004), http://www.intel.co.jp/
Intel 925X/925XE Express Chipset Datasheet (November 2004), http://www.intel.co.jp/
Hewson, D., Beecroft, J., Hewson, D., McLaren, M., Roweth, D.: QsNet II: Performance Evaluation (2003), http://www.quadrics.com/
Tanabe, N., Hamada, Y., Nakajo, H., Imashiro, H., Yamamoto, J., Kudoh, T., Amano, H.: Low latency communication on DIMMnet-1 network interface plugged into a DIMM slot. In: Parallel Computing in Electrical Engineering 2002, pp. 9–14 (2002)
Tanabe, N., Yamamoto, J., Hamada, Y., Nakajo, H., Kudoh, T., Amano, H.: BOTF:A High Bandwidth Communication Mechanism of DIMMnet-1 Network Interface Plugged into a DIMM slot. IPSJ Journal (2002)(In Japanese)
Liu, J., Mamidala, A., Vishnu, A., Panda, D.K.: Evaluating InfiniBand Performance with PCI Express. IEEE Micro 25(1), 20–29 (2005)
Beecroft, J., Addison, D., Hewson, D., McLaren, M., Petrini, F., Roweth, D.: Quadrics QsNetII: Pushing the Limit of the Design of High-Performance Networks for Supercomputers. IEEE Micro, (accepted for publication), Available from http://www.c3.lanl.gov/fabrizio/papers/ieeemicro-elan4.pdf
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Miyabe, Y. et al. (2008). Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. In: Labarta, J., Joe, K., Sato, T. (eds) High-Performance Computing. ISHPC ALPS 2005 2006. Lecture Notes in Computer Science, vol 4759. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77704-5_18
Download citation
DOI: https://doi.org/10.1007/978-3-540-77704-5_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77703-8
Online ISBN: 978-3-540-77704-5
eBook Packages: Computer ScienceComputer Science (R0)