Abstract
The MIPS® MT architecture is a fine-grained multithreading extension to the general-purpose MIPS RISC architecture. In addition to the classical multithreaded provision for explicit exploitation of cuncurrency as a mechanism for latency tolerance, MIPS MT has unique features to address the problems of real-time and embedded computing in System-on-a-Chip environments. This paper provides an overview of the MIPS MT architecture and how it can variously be exploited to improve computational bandwidth, real time quality of service, and response time to asynchronous events.
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Kissell, K.D. (2008). MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing. In: Stenström, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77560-7_2
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DOI: https://doi.org/10.1007/978-3-540-77560-7_2
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