Abstract
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed on every cache miss before any coherence action can be performed. In this work we present a new protocol that moves the role of storing up-to-date coherence information (and thus ensuring totally ordered accesses) from the home node to one of the sharing caches. Our protocol allows most cache misses to be directly solved from the corresponding remote caches, without requiring the intervention of the home node. In this way, cache miss latencies are reduced. Detailed simulations show that this protocol leads to improvements in total execution time of 8% on average over a highly optimized MOESI directory-based protocol.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Acacio, M.E., González, J., García, J.M., Duato, J.: Owner prediction for accelerating cache-to-cache transfer misses in cc-NUMA multiprocessors. In: SC2002. High Performance Networking and Computing (November 2002)
Acacio, M.E., González, J., García, J.M., Duato, J.: The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors. In: PACT 2002. 11th Int’l Conference on Parallel Architectures and Compilation Techniques, pp. 155–164 (September 2002)
Chang, J., Sohi, G.S.: Cooperative caching for chip multiprocessors. In: ISCA 2006. 33th Int’l Symp. on Computer Architecture, pp. 264–276 (June 2006)
Cheng, L., Carter, J.B., Dai, D.: An adaptive cache coherence protocol optimized for producer-consumer sharing. In: HPCA-13. 13th Int’l Symp. on High Performance Computer Architecture, pp. 328–339 (February 2007)
Culler, D.E., Singh, J.P., Gupta, A.: Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann Publishers, Inc, San Francisco (1999)
Gupta, A., Weber, W.-D., Mowry, T.C.: Reducing memory traffic requirements for scalable directory-based cache coherence schemes. In: ICPP 1990. Int’l Conference on Parallel Processing, pp. 312–321 (August 1990)
Hughes, C.J., Pai, V.S., Ranganathan, P., Adve, S.V.: RSIM: Simulating shared-memory multiprocessors with ILP processors. IEEE Computer 35(2), 40–49 (2002)
Martin, M.M.: Token Coherence. PhD thesis, University of Wisconsin-Madison (December 2003)
Martin, M.M., Hill, M.D., Wood, D.A.: Token coherence: Decoupling performance and correctness. In: ISCA 2003. 30th Int’l Symp. on Computer Architecture, pp. 182–193 (June 2003)
Martin, M.M., Sorin, D.J., Ailamaki, A., Alameldeen, A.R., Dickson, R.M., Mauer, C.J., Moore, K.E., Plakal, M., Hill, M.D., Wood, D.A.: Timestamp snooping: An approach for extending SMPs. In: ASPLOS IX. 9th Int’l Conference on Architectural Support for Programming Languages and Operating Systems, pp. 25–36 (November 2000)
Martin, M.M., Sorin, D.J., Hill, M.D., Wood, D.A.: Bandwidth adaptive snooping. In: HPCA-8. 8th Int’l Symp. on High-Performance Computer Architecture, pp. 251–262 (January 2002)
Nanda, A.K., Nguyen, A.-T., Michael, M.M., Joseph, D.J.: High-throughput coherence controllers. In: HPCA-6. 6th Int’l Symp. on High-Performance Computer Architecture, pp. 145–155 (January 2000)
Ros, A., Acacio, M.E., García, J.M.: A novel lightweight directory architecture for scalable shared-memory multiprocessors. In: Cunha, J.C., Medeiros, P.D. (eds.) Euro-Par 2005. LNCS, vol. 3648, pp. 582–591. Springer, Heidelberg (2005)
Ros, A., Acacio, M.E., García, J.M.: An efficient cache design for scalable glueless shared-memory multiprocessors. In: ACM Int’l Conference on Computing Frontiers, pp. 321–330 (2006)
Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: Characterization and methodological considerations. In: ISCA 1995. 22nd Int’l Symp. on Computer Architecture, pp. 24–36 (June 1995)
Wulf, W., McKee, S.: Hitting the memory wall: Implications of the obvious. Computer Architecture News 23(1), 20–24 (1995)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ros, A., Acacio, M.E., García, J.M. (2007). Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. In: Aluru, S., Parashar, M., Badrinath, R., Prasanna, V.K. (eds) High Performance Computing – HiPC 2007. HiPC 2007. Lecture Notes in Computer Science, vol 4873. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77220-0_17
Download citation
DOI: https://doi.org/10.1007/978-3-540-77220-0_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77219-4
Online ISBN: 978-3-540-77220-0
eBook Packages: Computer ScienceComputer Science (R0)