Abstract
Instruction sets may have particular characteristics that produce a negative impact into the amount of available parallelism. The x86 instruction set architecture includes some of those characteristics. In particular, it is well know the negative impact of condition codes usage. In a coarse approximation, they can be considered responsible for a greater code coupling. Moreover, several in-depth works show that they introduce additional complexity in the procedures both to perform microcode binary translation and to support for precise exception mechanisms among others. To the extent of our knowledge no quantitative evaluation has been carried out that may determine the impact of condition codes usage on the x86 processors performance. In this work we will present a proposal of such quantification based on Graph Theory.
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References
Biggs, N.L.: Algebraic Graph Theory, 2nd edn. Cambridge University Press, Cambridge (1993)
Bose, P.: Instruction Set Design for Support of High-Level Languages. Ph.D. Thesis, University of Illinois at Urbana-Champaign (1983)
Durán, R., Rico, R.: Quantification of ISA Impact on Superscalar Processing. In: Proceeding of EUROCON 2005, pp. 701–704 (2005)
Durán, R., Rico, R.: On applying graph theory to ILP analysis. IEEE Latin America Transactions, 289–296 (2006)
Godsil, C.D., Royle, G.F.: Algebraic Graph Theory. Springer, Heidelberg (2001)
Gschwind, M.: Method for the deferred materialization of condition code information. Research Disclosures (1999)
Gschwind, M., Ebcioglu, K., Altman, E., Sathaye, S.: Binary Translation and Architecture Convergence Issues for IBM System/390. In: Proceedings of the 14th International Conference on Supercomputing, pp. 336–347 (2000)
Hu, S., Smith, J.E.: Using Dynamic Binary Translation to Fuse Dependent Instructions. In: Proceedings of the International Symposium on Code Generation and Optimization CGO, pp. 213–224 (2004)
Huang, I.J., Peng, T.C.: Analysis of x86 Instruction Set Usage for DOS/Windows Applications and Its Implication on Superscalar Design. IEICE Transactions on Information and Systems E85-D(6), 929–939 (2002)
Hwu, W.W., Patt, Y.N.: Checkpoint repair for out-of-order execution machines. IEEE Transactions on Computers C-36, 1496–1514 (1987)
Kim, I., Lipasti, M.H.: Macro-op Scheduling: Relaxing Scheduling Loop Constraints. In: Proceedings of the 36th International Symposium on Microarchitecture, pp. 1496–1514 (2003)
Maurer, W.D.: A theory of computer instructions. Journal of the ACM 13(2), 226–235 (1966)
Mutlu, O., Stark, J., Wilkerson, C., Patt, Y.N.: Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors. In: Proc. of the 9th Intl. Symp. on High-Performance Computer Architecture, pp. 129–140 (2003)
Rico, R., Pérez, J.I., Frutos, J.A.: The impact of x86 instruction set architecture on superscalar processing. Journal of Systems Architecture 51.1 (2005)
Skadron, K., Martonosi, M., August, D.I., Hill, M.D., Hill, D.J., Pai, V.S.: Challenges in Computer Architecture Evaluation. IEEE Computer 36.8 (2003)
Sohi, G.S.: Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers. IEEE Transactions on Computers, 349–359 (1990)
Stark, J., Brown, M.D., Patt, Y.N.: On Pipelining Dynamic Instruction Scheduling Logic. In: Proc. of the 33rd Annual ACM/IEEE Intl. Symp. on Microarchitecture, pp. 57–66 (2000)
Stefanovic, D., Martonosi, M.: Limits and Graph Structure of Available Instruction-Level Parallelism. In: Proceedings of the European Conference on Parallel Computing (2000)
Wall, D.W.: Limits of instruction-level parallelism. In: Proc. of the 4th Intl. Conference on Architectural Support for Programming Languages and Operating Systems, pp. 176–188 (1991)
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Escuder, V., Durán, R., Rico, R. (2007). Analysis of x86 ISA Condition Codes Influence on Superscalar Execution. In: Aluru, S., Parashar, M., Badrinath, R., Prasanna, V.K. (eds) High Performance Computing – HiPC 2007. HiPC 2007. Lecture Notes in Computer Science, vol 4873. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77220-0_15
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DOI: https://doi.org/10.1007/978-3-540-77220-0_15
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