Abstract
HDTV based applications require FSBM to maintain its significantly higher resolution than traditional broadcasting formats (NTSC, SECAM, PAL). This paper proposes some techniques to increase the speed and reduce the area requirements of an FSBM hardware. These techniques are based on modifications of the Sum-of-Absolute-Differences (SAD) computation and the MacroBlock (MB) searching strategy. The design of an FSBM architecture based on the proposed approaches has also been outlined. The highlight of the proposed architecture is its split pipelined design to facilitate parallel processing of macroblocks (MBs) in the initial stages. The proposed hardware has high throughput, low silicon area and compares favorably with other existing FPGA architectures.
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References
Ghanbari, M.: Standard Codecs: Image Compression to Advanced Video Coding. IEE (2003)
Loukil, H., Ghozzi, F., Samet, A., Ben Ayed, M., Masmoudi, N.: Hardware implementation of block matching algorithm with fpga technology. In: Proc. Intl. Conf. on Microelectronics, pp. 542–546 (2004)
Mohammadzadeh, M., Eshghi, M., Azadfar, M.: Parameterizable implementation of full search block matching algorithm using fpga for real-time applications. In: Proc. 5th IEEE Intl. Caracas Conf. on Dev., Circ. and Sys., Dominican Republic, pp. 200–203 (2004)
Olivares, J., Hormigo, J., Villalba, J., Benavides, I., Zapata, E.: Sad computation based on online arithmetic for motion estimation. Jrnl. Microproc. and Microsys. 30, 250–258 (2006)
Roma, N., Dias, T., Sousa, L.: Customisable core-based architectures for real-time motion estimation on fpgas. In: Proc. of 3rd Intl. Conf. on Field Prog. Logic and Appl., pp. 745–754 (2003)
Ryszko, A., Wiatr, K.: An assesment of fpga suitability for implementation of real-time motion estimation. In: Proc. IEEE Euromicro Symp. on DSD, pp. 364–367 (2001)
Wong, S., S., V., Cotofona, S.: A sum of absolute differences implementation in fpga hardware. In: Proc. 28th Euromicro Conf., pp. 183–188 (2002)
Komarek, T., Pirsch, P.: Array archtectures for block matching algorithms. IEEE Circ. and Sys. 36(10), 1301–1308 (1989)
Vos, L., Stegherr, M.: Parameterizable vlsi architectures for the full- search block- matching algorithm. IEEE Circ. and Sys. 36(10), 1309–1316 (1989)
Yang, K., Sun, M., Wu, L.: A family of vlsi designs for the motion compensation block-matching algorithm. IEEE Circ. and Sys. 36(10), 1317–1325 (1989)
Hsieh, C., Lin, T.: Vlsi architecture for block-matching motion estimation algorithm. IEEE Tran. Circ. and Sys. Video Tech. 2(2), 169–175 (1992)
Jehng, Y., Chen, L., Chiueh, T.: Efficient and simple vlsi tree architecture for motion estimation algorithms. IEEE Tran. Sig. Pro. 41(2), 889–899 (1993)
Yeo, H., Hu, Y.: A novel modular systolic array architecture for full-search blockmatching motion estimation. In: Proc. Intl. Conf. on Acou. Speech, and Sig. Proc., vol. 5, pp. 3303–3306 (1995)
Lai, Y., Chen, L.: A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm. IEEE Tran. Circ. and Sys. Video Tech. 8(2), 124–127 (1998)
Yeh, Y., Lee, C.: Cost-effective vlsi architectures and buffer. size optimization for full-search block matching algorithms. IEEE Tran. VLSI Sys. 7(3), 345–358 (1999)
Sousa, L., Roma, N.: Low-power array architectures for motion estimation. In: IEEE 3rd Workshop on Mult. Sig. Proc., pp. 679–684 (1999)
Do, V., Yun, K.: A low-power vlsi architecture for full-search block-matching. IEEE Tran. Circ. and Sys. Video Tech. 8(4), 393–398 (1998)
Lin, S., Tseng, P., Chen, L.: Low-power parallel tree architecture for full search block-matching motion estimation. In: Proc. of Intl. Symp. Circ. and Sys., vol. 2, pp. 313–316 (2004)
Salomon, D.: Data Compression: The Complete Reference, 3rd edn. Springer, New York (2004)
Tuan, J., Jen, C.: An architecture of full-search block matching for minimum memory bandwidth requirement. In: Proceedings of the IEEE GLSVLSI, pp. 152–156 (1998)
Weblink: Famous equations and inequalities. http://www.math.utah.edu/pa/math/equations/equations.html (2006)
Efimov, A., Zolotarev, Y., Terpigoreva, V.: Mathematical Analysis (Advanced Topics). Mir Publishers, Moscow (1985)
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Saha, A., Ghosh, S. (2007). A Speed-Area Optimization of Full Search Block Matching Hardware with Applications in High-Definition TVs (HDTV). In: Aluru, S., Parashar, M., Badrinath, R., Prasanna, V.K. (eds) High Performance Computing – HiPC 2007. HiPC 2007. Lecture Notes in Computer Science, vol 4873. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77220-0_12
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DOI: https://doi.org/10.1007/978-3-540-77220-0_12
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