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Efficient Implementations of Some Tweakable Enciphering Schemes in Reconfigurable Hardware

  • Cuauhtemoc Mancillas-López
  • Debrup Chakraborty
  • Francisco Rodríguez-Henríquez
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4859)

Abstract

We present optimized FPGA implementations of three tweakable enciphering schemes, namely, HCH, HCTR and EME using AES-128 as the underlying block cipher. We report performance timings and hardware resources occupied by these three modes when using a fully pipelined AES core and a sequential AES design. Our experimental results suggest that in terms of area HCTR, HCH and HCHfp (a variant of HCH) require more area than EME. However, HCTR performs the best in terms of speed followed by HCHfp, EME and HCH.

Keywords

Hash Function Clock Cycle Block Cipher Counter Mode Message Length 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Cuauhtemoc Mancillas-López
    • 1
  • Debrup Chakraborty
    • 1
  • Francisco Rodríguez-Henríquez
    • 1
  1. 1.Computer Science Departament, Centro de Investigación y Estudios Avanzados del IPN, Av. Instituto Politécnico Nacional No. 2508, México D.F. 

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