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Design of a Differential Power Analysis Resistant Masked AES S-Box

  • Kundan Kumar
  • Debdeep Mukhopadhyay
  • Dipanwita RoyChowdhury
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4859)

Abstract

Gate level masking is one of the most popular countermeasures against Differential Power Attack (DPA). The present paper proposes a masking technique for AND gates, which are then used to build a balanced and masked multiplier in GF(2 n ). The circuits are shown to be computationally secure and have no glitches which are dependent on unmasked data. Finally, the masked multiplier in GF(24) is used to implement a masked AES S-Box in GF(24)2. Power measurements are taken to support the claim of random power consumption.

Keywords

Power Consumption Advance Encryption Standard Primitive Polynomial Differential Power Analysis Critical Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Kundan Kumar
    • 1
  • Debdeep Mukhopadhyay
    • 2
  • Dipanwita RoyChowdhury
    • 3
  1. 1.MTech Student, Department of Computer Science and Engg., Indian Institute of Technology, KharagpurIndia
  2. 2.Assistant Professor, Department of Computer Science and Engg., Indian Institute of Technology, MadrasIndia
  3. 3.Professor, Department of Computer Science and Engg., Indian Institute of Technology, KharagpurIndia

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