Abstract
A high-performance and dynamic reconfigurable modular arithmetic unit is presented, which provides full support to modulo 28/216/232 addition and modulo232/ 216+1/232-1 multiplication operation. To save the hardware cost, we have adopted sharing technique to implement modular multiplication operation, and then optimized each critical block. The design has been realized using Altera’s FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18μm SMIC process. The result proves that the propagation time of the critical path is 6.04ns. Compared with other designs, the reconfigurable modular arithmetic unit not only supports for diverse modular arithmetic in the block ciphers, but also provides IP Core for reconfigurable cryptographic system.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Booth, A.D.: A Signed Binary Multiplication Technique. Quarterly Journal of Mechanics and Applied Mathematics 4, 236–240 (1951)
Nan, Y.S., Chen, O.T.: Low-power multipliers by minimizing switching activities of partial products. In: IEEE International Symposium on Circuits and Systems[C]. IEEE Circuits and Systems Society, Arizona USA, pp. 93–96 (2002)
Ling, H.: High-Speed Binary Adder. IBM Journal of Research and Development 25, 156–166 (1981)
Ying jie Qu.: The Research and Design of the Reconfigurable Logic for Cryptography[D]. In: Beijing University of Technology, Beijing China (2002)
Elbirt, A.J.: Reconfigurable Computing For Symmetric-Key Algorithms[D] Massachusetts: Electrical and Computer Engineering Department University of Massachusetts Lowell (2002)
Yu tai Ma: A Simplified Architecture for Modulo (2n + 1) Multiplication. IEEE Transactions on Computers 47 (1998)
MacSorley, O.L.: High-Speed Arithmetic in Binary Computers. Proceedings of the IRE 49, 67–91 (1961)
Weinberger, A., Smith, J.L.: A One-Microsecond. Adder Using One-Megacycle Circuitry. IRE Transactions on Electronic Computers, 65–73 (1956)
Wallace, C.S.: A Suggestion for a Fast Multiplier. IEEE Transactions on Electronic Computers, 14–17 (1964)
Brent, P.R., Kung, T.H.: A regular layout for parallel adders. IEEE Trans. Comput. 32, 260–264 (1982)
Kogge, P., Stone, H.: A parallel algorithm for the efficient solution. IEEE Trans. Comput. 22, 783–787 (1973)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Li, W., Dai, Z., Chen, T., Meng, T., Yang, X. (2007). Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit. In: Xu, M., Zhan, Y., Cao, J., Liu, Y. (eds) Advanced Parallel Processing Technologies. APPT 2007. Lecture Notes in Computer Science, vol 4847. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-76837-1_9
Download citation
DOI: https://doi.org/10.1007/978-3-540-76837-1_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-76836-4
Online ISBN: 978-3-540-76837-1
eBook Packages: Computer ScienceComputer Science (R0)