Abstract
Memory-Space-Memory (MSM) Clos packet switching networks are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Clos networks had been studied and applied quite well in circuit switching system, with much attentions paid to its non-blocking property to decrease call blocking rates. In contrast, for packet switching systems, more care is taken to per-packet based forwarding performance of the switching networks. MSM Clos network has the merit of keeping packet sequence and therefore is quiet adapt to packet switching fabric. By way of buffering architecture, MSM Clos network is quite similar to the CIOQ Crossbar based single stage switching fabric, which promotes us to extend the results of CIOQ matching an OQ switch [1] to MSM Clos networks. Meanwhile, although the CIOQ switch can emulate an OQ switch, it needs cell insertion algorithm and stable matching algorithm with high information complexity and computing complexity. This has prevented its application seriously in new generation of routers with high speed linking rates and large port numbers. So we propose a new method of Per-Input OQ Emulation (PIOE), including both new cell insertion and scheduling algorithm (PVPP-CIP and -CSP) with only per-input local information and new matching algorithm (S 3) with computing complexity of O(1), which is more practical in both CIOQ Crossbar and MSM Clos networks.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Chuang, S.T., Awadallah, A., McKeown, N., Prabhakar, B.: Matching output queueing with a combined input and output queued switch. IEEE Journal on Selected Areas in Communicaions 17, 1030–1039 (1999)
Chao, H.J.: Next generation routers. IEEE Proceeding 90(9), 1518–1558 (2002)
McKeown, N.: The iSLIP Scheduling Algorithm for Input-Queued Switches. IEEE/ACM Trans. on Networking 7(2) (1999)
McKeown, N., Anntharam, V., Walrand, J.: Achieving 100% Throughput in an input-queued switch. In: Infocom 1996 (1996)
Wang, F., Hamdi, M.: Analysis on the Central-stage Buffered Clos-network for packet switching. In: IEEE International Conference on Communications (2005)
Clos, C.: A Study of Non-Blocking Switching Networks. Bell Systems Technical Journal, 406–424 (1953)
Tsai, K.H., wang, D.W.: Lower Bounds for Wide-sense Non-Blocking Clos Network. In: Taipei 1998. Computing and Combinatorics, Springer, Berlin, pp. 213–218 (1998)
Lee, T.T., To, P.P.: Non-Blocking Routing Properties of Clos Networks. In: Advances in switching networks, Amer. Math. Soc., Providence, RI, pp. 181–195 (1998)
Lin, G.H., Du, D.Z., Wu, W., Yoo, K.: On 3-Rate Rearrangeability of Clos Networks. In: Advances in switching networks, Amer. Math. Soc., Providence, RI, Princeton, NJ, pp. 315–333 (1998)
Lee, T.T., Lam, C.H.: Path Switching - A Quasi-Static Routing Scheme for Large-Scale ATM Packet Switches. IEEE J. Select. Areas Communications. 15, 914–924 (2002)
Pun, K., Hamdi, M.: Distro: A Distributed Static Round-Robin Scheduling Algorithm for Bufferless Clos-Network Switches. IEEE GLOBECOM (2002)
Chao, H.J., Deng, K-L., Jing, Z.: A Petabit Photonic Packet Switch (P3S). IEEE INFOCOM 2003 (2003)
Gale, D., Shapley, L.S.: College Admissions and the Stability of Marriage. American Mathematical Monthly 69, 9–15 (1962)
Iyer, S., Awadallah, A., McKeown, N.: Analysis of a Packet Switch with Memories Running Slower than the Line Rate. In: IEEE Infocom 2000 (2000)
Demers, A., Keshav, S., Shenker, S.: Analysis and Simulation of a Fair Queueing Algorithm. J. Internetworking: Research and Experience, 3–26 (1990)
Parekh, A., Gallager, R.: A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single Node Case. IEEE/ACM Trans. Networking 1, 344–357 (1993)
Zhang, L.: Virtual Clock: A New Traffic Control Algorithm for Packet Switching Networks. ACM Trans. Comput. Syst. 9(2), 101–124 (1990)
Shreedhar, M., Varghese, G.: Efficient Fair Queueing Using Deficit Round Robin. In: Proc. ACM SIGCOMM, pp. 231–242. ACM Press, New York (1995)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ma, X., Hu, Y., Mao, J., Lan, J., Guan, L., Zhang, B. (2007). Analysis on Memory-Space-Memory Clos Packet Switching Network. In: Xu, M., Zhan, Y., Cao, J., Liu, Y. (eds) Advanced Parallel Processing Technologies. APPT 2007. Lecture Notes in Computer Science, vol 4847. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-76837-1_25
Download citation
DOI: https://doi.org/10.1007/978-3-540-76837-1_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-76836-4
Online ISBN: 978-3-540-76837-1
eBook Packages: Computer ScienceComputer Science (R0)