Abstract
The multiply clock domain (MCD) technique is a novel technique to compromising between synchronous systems and asynchronous systems to reduce the power. However, most present studies of MCD are based on superscalar architectures. In this paper, MCDE, a MCD technique based on explicitly parallel instruction computing (EPIC) architecture is designed and implemented to reduce the power of clock distribution network. In addition, a series of experiments have been done to evaluate it. The result of the experiments show that, using a MCDE clock network microarchitecture with a fine-grained adaptive dynamic adjustment algorithm, can effectively decrease the microprocessor power by 40%, compared with the original EPIC clock network microarchitecture.
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Keywords
- Asynchronous Communication
- Very Long Instruction Word
- Asynchronous System
- Synchronous System
- Annual International Symposium
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References
Pangjun, J., et al.: Low-Power Clock Distribution Using Multiple Voltages and Reduced Swings. IEEE Trans.on VLSI systems 10(3), 309–318 (2002)
Chapiro, D.M.: Globally Asynchronous Locally Synchronous Systems. PhD thesis, Stanford Univ. (1984)
Iyer, A., Marculescu, D.: Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. In: Proceedings of the 29th Annual International Symposium on Computer Architecture, pp. 158–170 (2002)
Magklis, G., et al.: Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. In: Proceedings of the 30th Annual International Symposium on Computer Architecture, pp. 14–27 (2003)
Semeraro, G., Magklis, G., et al.: Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In: Proc. 9th Int’l Symp. High-Performance Computer Architecture, pp. 29–40 (2002)
Semeraro, G., Albonesi, D.H., et al.: Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture. In: Proc. 35th Ann. IEEE/ACM Int’l Symp. Microarchitecture, pp. 356–370 (2002)
Iyer, A., Marculescu, D.: Power efficiency of voltage scaling in multiple clock, multiple voltage cores. In: Proceedings of the International Conference on Computer-Aided Design, pp. 379–386 (2002)
Eswaran, A., Chen, S.: All-domain fine grain dynamic speed/voltage scaling for GALS processors (2003), URL: http://www.ece.cmu.edu/~schen1/ece743/proposal_up.pdf
Schlansker, M., Rau, B.: EPIC: Explicitly Parallel Instruction Computing. IEEE Computer 33(2), 37–45 (2000)
Naffziger, S., Colon-Bonet, G., Fischer, T., et al.: The Implementation of the Itanium 2 Microprocessor. IEEE Journal of Solid-State Circuits 37(11), 1448–1460 (2002)
Schlansker, M., Rau, B.: EPIC An Architecture for Instruction-Level Parallel Processors. Technical Report HPL-1999-111, HP Laboratories (2000)
Reinman, G., Jouppi, N.: An Integrated Cache Timing and Power Model. Technical report 2000/7, Western Research Laboratory, USA (2000)
Yongwen, W., Minxuan, Z.: Microarchitecture-Level Power Modeling and Analyzing for High-Performance Microprocessors. Chinese Journal of Computers 27(10), 1320–1327 (2004)
Yongwen, W., Minxuan, Z.: IMPACT: XP: An integrated performance / power analysis framework for compiler and architecture research. Chinese Journal of Electronics 13(2), 250–253 (2004)
Chang, P., Mahlke, S., Chen, W., et al.: An Architectural Framework for Multiple-instruction-issue Processors. In: Proceedings of the 18th Annual International Symposium on Computer Architecture, pp. 266–275 (1991)
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Ji, R., Zeng, X., Chen, L., Zhang, J. (2007). The Implementation and Evaluation of a Low-Power Clock Distribution Network Based on EPIC. In: Li, K., Jesshope, C., Jin, H., Gaudiot, JL. (eds) Network and Parallel Computing. NPC 2007. Lecture Notes in Computer Science, vol 4672. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74784-0_48
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DOI: https://doi.org/10.1007/978-3-540-74784-0_48
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