Abstract
Register file design is very important in high performance processor design. Register Stack and Register Rotation are effective ways to improve performance. Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. SMT(simultaneous multithreading) processors execute instructions from different threads in the same cycle, which has the unique ability to exploit ILP(instruction-level parallelism) and TLP(thread-level parallelism) simultaneously. EPIC(explicitly parallel instruction computing) emphasizes importance of the synergy between compiler and hardware. In this paper, we present our efforts to design and implement register file management mechanism on a parallel environment, which includes an optimizing, portable parallel compiler OpenUH and SMT architecture EDSMT based on IA-64. Meanwhile, its compile optimization is also considered to improve the performance.
This work was supported by “863” project No. 2002AA110020, Chinese NSF No. 60376018, No. 60273069 and No. 90207011.
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References
Tullsen, D., Eggers, S., Levy, H.: Simultaneous Multithreading: Maximizing On- Chip Parallelism. In: The 22rd Annual International Symposium on Computer Architecture (ISCA), pp. 392–403 (1995)
Olukotun, K., Nayfeh, B.A., Hammond, L., Wilson, K., Chang, K.: The Case for a Single-Chip Multiprocessor. SIGOPS Oper. Syst. Rev. 30(5), 2–11 (1996)
Li, Y., Brooks, D., Hu, Z., Skadron, K., Bose, P.: Understanding the Energy Efficiency of Simultaneous Multithreading. In: The 2004 International Symposium on Low Power Electronics and Design, pp. 44–49 (2004)
Sasanka, R., Adve, S.V., Chen, Y.-K., Debes, E.: The Energy Efficiency of CMP vs. SMT for Multimedia Workloads. In: The 18th Annual International Conference on Supercomputing, pp. 196–206 (2004)
Kaxiras, S., Narlikar, G., Berenbaum, A.D., Hu, Z.: Comparing Power Consumption of an SMT and a CMP DSP for Mobile Phone Workloads. In: The 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 211–220 (2001)
Li, Y., Skadron, K., Hu, Z., Brooks, D.: Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. In: The Eleventh IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 71–82. IEEE Computer Society Press, Los Alamitos (2005)
Itanium Processor Microarchitecture Reference: for Software Optimization 05 (2002), http://www.developer.intel.com/design/ia64/itanium.htm
Jianhua, Y., Hongmei, W.: Actuality and Trend of Parallel Language and Compilation. Computer Engineering, pp. 97–98 (December 2004)
OpenUH: An Optimizing, Portable OpenMP Compiler (2006), http://www2.cs.uh.edu/copper/pubs.html
Akkary, H., Driscoll, M.A.: A dynamic multithreading processor. In: The 31st annual ACM/IEEE international symposium on Microarchitecture, pp. 226–236 (1998)
Schlansker, M.S., Rau, B.R.: EPIC: Explicitly Parallel Instruction Computing[J]. IEEEComputer 32(2), 37–45 (2000)
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Deng, Q., Zhang, M., Jiang, J. (2007). Register File Management and Compiler Optimization on EDSMT. In: Thulasiraman, P., He, X., Xu, T.L., Denko, M.K., Thulasiram, R.K., Yang, L.T. (eds) Frontiers of High Performance Computing and Networking ISPA 2007 Workshops. ISPA 2007. Lecture Notes in Computer Science, vol 4743. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74767-3_41
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DOI: https://doi.org/10.1007/978-3-540-74767-3_41
Publisher Name: Springer, Berlin, Heidelberg
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