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Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression

  • Yunbi Chen
  • Jingsong He
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4684)

Abstract

The way combining intelligent technology with hardware technology to study real-world applications is one of the most important methodologies in the field of EHW. This paper designs a novel evolvable hardware engine for predictive lossless image compression in the perspective of hardware, and firstly implements the whole engine on reconfigurable hardware. As a result of the high-speed pipeline architecture, all the modules of this engine can process the data in parallel. For the most time-consuming fitness evaluation unit, the systolic array which essentially accelerate the fitness evaluation is employed. Experimental results show that the proposed evolvable hardware engine can reduce the computing time remarkably (the speedup ratio approximates to 500), and can fully utilize the hardware resources. The systolic technique adopted here also promises to scale up images size with comparatively slower speed of the increasing of the power consumption.

Keywords

Evolvable Hardware Fitness Evaluation Systolic Array Image Compression 

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References

  1. 1.
    Yao, X., Higuchi, T.: Promises and challenges of evolvable hardware. IEEE Transactions on Systems, Man and Cybernetics, Part C 29(1), 87–97 (1999)CrossRefGoogle Scholar
  2. 2.
    Hirst, A.J.: Notes on the evolution of adaptive hardware. In: Parmee, I. (ed.) Proceeding of Second International Conference on Adaptive Computing in Engineering Design and Control, pp. 212–219. University of Plymouth, UK (1996)Google Scholar
  3. 3.
    Higuchi, T., Iwata, M., Kajitani, I., Iba, H., Hirao, Y., Furuya, T., Manderick, B.: Evolvable Hardware and Its Applications to Pattern Recognition and Fault-Tolerant Systems. In: Sanchez, E., Tomassini, M. (eds.) Towards Evolvable Hardware. LNCS, vol. 1062, pp. 118–135. Springer, Heidelberg (1996)Google Scholar
  4. 4.
    Koza, J., Bennett III., F., Andre, D., Keane, M., Dunlap, F.: Automated synthesis of analog electrical circuits by means ofgenetic programming. IEEE Transactions on Evolutionary Computation 1(2), 109–128 (1997)CrossRefGoogle Scholar
  5. 5.
    Thompson, A., Koza, J., Goldberg, D., Fogel, D., Riolo, R.: Silicon Evolution. In: Genetic Programming 1996: Proceedings of the First Annual Conference, pp. 444–452 (1996)Google Scholar
  6. 6.
    Higuchi, T., Murakawa, M., Iwata, M., Kajitani, I., Liu, W., Salami, M.: Evolvable hardware at function level. In: IEEE International Conference on Evolutionary Computation, pp. 187–192 (1997)Google Scholar
  7. 7.
    Sakanashi, H., Iwata, M., Higuchi, T.: A Lossless Compression Method for Halftone Images Using Evolvable Hardware. In: Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware, pp. 314–326 (2001)Google Scholar
  8. 8.
    Fukunaga, A., Hayworth, K., Stoica, A.: Evolvable hardware for spacecraft autonomy. In: 1998 IEEE Aerospace Conference, Aspen, CO, pp. 135–143 (1998)Google Scholar
  9. 9.
    Fukunaga, A., Stechert, A., Koza, J., Banzhaf, W., Chellapilla, K., Deb, K., Dorigo, M., Fogel, D., Garzon, M., Goldberg, D., et al.: Evolving Nonlinear Predictive Models for Lossless Image Compression with Genetic Programming. In: Genetic Programming 1998: Proceedings of the Third Annual Conference, pp. 95–102 (1998)Google Scholar
  10. 10.
    He, J., Yao, X., Tang, J.: Towards intrinsic evolvable hardware for predictive lossless image compression. In: Wang, T.-D., Li, X., Chen, S.-H., Wang, X., Abbass, H., Iba, H., Chen, G., Yao, X. (eds.) SEAL 2006. LNCS, vol. 4247, pp. 632–639. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  11. 11.
    Shackleford, B., Snider, G., Carter, R., Okushi, E., Yasuda, M., Seo, K., Yasuura, H.: A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. Genetic Programming and Evolvable Machines 2(1), 33–60 (2001)zbMATHCrossRefGoogle Scholar
  12. 12.
    Tufte, G., Haddow, P.: Prototyping a GA Pipeline for complete hardware evolution. In: Evolvable Hardware, 1999. Proceedings of the First NASA/DoD Workshop on, pp. 18–25 (1999)Google Scholar
  13. 13.
    Glette, K., Torresen, J.: A Flexible On-chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. In: Moreno, J.M., Madrenas, J., Cosp, J. (eds.) ICES 2005. LNCS, vol. 3637, pp. 66–75. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  14. 14.
    Koza, J.R., Bennett III, F.H., Hutchings, J.L., Bade, S.L., Keane, M.A., Andre, D.: Evolving sorting networks using genetic programming and rapidly reconfigurable field-programmable gate arrays. In: Higuchi, T. (ed.) Workshop on Evolvable Systems. International Joint Conference on Artificial Intelligence, Nagoya, pp. 27–32 (1997)Google Scholar
  15. 15.
    Yamaguchi, Y., Miyashita, A., Maruyama, T., Hoshino, T.: A co-processor system with a virtex fpga for evolutionary computation. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 240–249. Springer, Heidelberg (2000)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Yunbi Chen
    • 1
  • Jingsong He
    • 2
  1. 1.Department of Electronic Science and Technology 
  2. 2.Nature Inspired Computation and Applications Laboratory, University of Science and Technology of China, Hefei, 230026China

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