Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression

  • Yunbi Chen
  • Jingsong He
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4684)


The way combining intelligent technology with hardware technology to study real-world applications is one of the most important methodologies in the field of EHW. This paper designs a novel evolvable hardware engine for predictive lossless image compression in the perspective of hardware, and firstly implements the whole engine on reconfigurable hardware. As a result of the high-speed pipeline architecture, all the modules of this engine can process the data in parallel. For the most time-consuming fitness evaluation unit, the systolic array which essentially accelerate the fitness evaluation is employed. Experimental results show that the proposed evolvable hardware engine can reduce the computing time remarkably (the speedup ratio approximates to 500), and can fully utilize the hardware resources. The systolic technique adopted here also promises to scale up images size with comparatively slower speed of the increasing of the power consumption.


Evolvable Hardware Fitness Evaluation Systolic Array Image Compression 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Yunbi Chen
    • 1
  • Jingsong He
    • 2
  1. 1.Department of Electronic Science and Technology 
  2. 2.Nature Inspired Computation and Applications Laboratory, University of Science and Technology of China, Hefei, 230026China

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