Improving Flexibility in On-Line Evolvable Systems by Reconfigurable Computing

  • Jim Torresen
  • Kyrre Glette
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4684)


Reconfigurable logic is a promising technology for adaptable systems – often called reconfigurable computing. However, one of the main challenges with autonomous adaptable systems is the flexibility. The paper starts with giving an overview of reconfigurable computing and different approaches to how it can be implemented. Then, we outline how these can be applied in on-line evolvable systems to improve flexibility in the hardware. The challenge of the latter is to include flexibility without re-synthesis and avoid having a too large logic gate overhead. An architecture based on system-on-chip and partial reconfiguration is proposed in the paper.


Functional Unit Context Switching Evolvable Hardware Reconfigurable Computing Xilinx FPGAs 
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  1. 1.
    Prophet, G.: FPGAs + the Internet = upgradable Product. In: EDN Europe, pp. 28–38 (2000)Google Scholar
  2. 2.
    Torresen, J.: An evolvable hardware tutorial. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 682–691. Springer, Heidelberg (2004)Google Scholar
  3. 3.
    Compton, K., Hauck, S.: Reconfigurable computing: A survey of systems and software. ACM Computing Surveys 34(2), 171–210 (2002)CrossRefGoogle Scholar
  4. 4.
    Steiger, C., Walder, H., Platzner, M.: Operating systems for reconfigurable embedded platforms: Online scheduling of real-time tasks. IEEE Trans. on Computers 53(11), 1393–1407 (2004)CrossRefGoogle Scholar
  5. 5.
  6. 6.
  7. 7.
  8. 8.
    Sekanina, L., Ruzicka, R.: Design of the special fast reconfigurable chip using common FPGA. In: IEEE DDECS 2000. Proc. of Design and Diagnostics of Electronic Circuits and Systems, pp. 161–168 (2000)Google Scholar
  9. 9.
    Torresen, J., Vinger, K.A.: High performance computing by context switching reconfigurable logic. In: ESM 2002. Proc. of the 16th European Simulation Multiconference, June 2002, pp. 207–210. SCS Europe (2002)Google Scholar
  10. 10.
    Vinger, K.A., Torresen, J.: Implementing evolution of FIR-filters efficiently in an FPGA. In: Proc. of the 2003 NASA/DoD Workshop on Evolvable Hardware (2003)Google Scholar
  11. 11.
    Torresen, J., Jakobsen, J.: An FPGA implemented processor architecture with adaptive resolution. In: AHS-2006. Proc. of 1st NASA/ESA Conference on Adaptive Hardware and Systems, IEEE Computer Society Press, Los Alamitos (2006)Google Scholar
  12. 12.
    Two flows for partial reconfiguration: module based or small bit manipulation, Application Note 290. Xilinx (2004)Google Scholar
  13. 13.
    Torresen, J.: Reconfigurable logic applied for designing adaptive hardware systems. In: SSGRR 2002W. Proc. of the International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet. Scuola Superiore G. Reiss Romoli (2002)Google Scholar
  14. 14.
    Hubner, M., et al.: New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits. In: ISVLSI 2006. Proc. of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, pp. 97–102. IEEE Computer Society Press, Los Alamitos (2006)Google Scholar
  15. 15.
    Upegui, A., Sanchez, E.: Evolving hardware by dynamically reconfiguring Xilinx FPGAs. In: Moreno, J.M., Madrenas, J., Cosp, J., et al. (eds.) ICES 2005. LNCS, vol. 3637, pp. 56–65. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  16. 16.
    Upegui, A., Sanchez, E.: Evolving hardware with self-reconfigurable connectivity in Xilinx FPGAs. In: Stoica, A., et al. (eds.) AHS-2006. Proceedings of the 1st NASA /ESA Conference on Adaptive Hardware and Systems, Los Alamitos, CA, USA, pp. 153–160. IEEE Computer Society Press, Los Alamitos (2006)Google Scholar
  17. 17.
    Glette, K., Torresen, J., Yasunaga, M.: An online EHW pattern recognition system applied to face image recognition. In: Giacobini, M., et al. (eds.) EvoWorkshops 2007. LNCS, vol. 4448, pp. 271–280. Springer, Heidelberg (2007)Google Scholar
  18. 18.
    Glette, K., Torresen, J., Yasunaga, M.: An online EHW pattern recognition system applied to sonar spectrum classification. In: ICES 2007 (to be published, 2007)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Jim Torresen
    • 1
  • Kyrre Glette
    • 1
  1. 1.Department of Informatics, University of Oslo, P.O. Box 1080 Blindern, N-0316 OsloNorway

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