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Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel

  • Jin Wang
  • Chang Hao Piao
  • Chong Ho Lee
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4684)

Abstract

To conquer the scalability issue of evolvable hardware, this paper proposes a multi-virtual reconfigurable circuit (VRC) cores-based evolvable system to evolve combinational logic circuits in parallel. The basic idea behind the proposed scheme is to divide a combinational logic circuit into several sub-circuits, and each of them is evolved independently as a subcomponent by its corresponding VRC core. The virtual reconfigurable circuit architecture is designed for implementing real-world applications of evolvable hardware (EHW) in common FPGAs. In our approach, all the VRC cores are realized in a Xilinx Virtex xcv2000E FPGA as an evolvable system to achieve parallel evolution. The proposed method is evaluated on the evolutions of 3-bit multiplier and adder and compared to direct evolution and incremental evolution in the terms of computational effort and hardware implementation cost.

Keywords

Intrinsic evolvable hardware scalability parallel evolutionary algorithm incremental evolution 

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References

  1. 1.
    Torresen, J.: Possibilities and Limitations of Applying Evolvable Hardware to Real-world Application. In: Proc. of the 10th International Conference on Field Programmable Logic and Applications, FPL-2000, Villach, Austria, pp. 230–239 (2000)Google Scholar
  2. 2.
    Yao, X., Higuchi, T.: Promises and Challenges of Evolvable Hardware. IEEE Transactions on Systems, Man, and Cybernetics 29(1), 87–97 (1999)CrossRefGoogle Scholar
  3. 3.
    Torresen, J.: A Divide-and-Conquer Approach to Evolvable Hardware. In: Sipper, M., Mange, D., Pérez-Uribe, A. (eds.) ICES 1998. LNCS, vol. 1478, pp. 57–65. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  4. 4.
    Torresen, J.: Evolving Multiplier Circuits by Training Set and Training Vector Partitioning. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 228–237. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  5. 5.
    Wang, J., et al.: Using Reconfigurable Architecture-Based Intrinsic Incremental Evolution to Evolve a Character Classification System. In: Hao, Y., Liu, J., Wang, Y.-P., Cheung, Y.-m., Yin, H., Jiao, L., Ma, J., Jiao, Y.-C. (eds.) CIS 2005. LNCS (LNAI), vol. 3801, pp. 216–223. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  6. 6.
    Murakawa, M., et al.: Hardware Evolution at Function Level. In: Ebeling, W., Rechenberg, I., Voigt, H.-M., Schwefel, H.-P. (eds.) PPSN IV 1996. LNCS, vol. 1141, pp. 62–71. Springer, Heidelberg (1996)Google Scholar
  7. 7.
    Zhang, Y., et al.: Digital Circuit Design Using Intrinsic Evolvable Hardware. In: Proc. Of the 2004 NASA/DoD Conference on the Evolvable Hardware, pp. 55–63. IEEE Computer Society Press, Los Alamitos (2004)CrossRefGoogle Scholar
  8. 8.
    Sekanina, L.: Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 186–197. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    Sekanina, L.: Evolutionary Design of Digital Circuits: Where Are Current Limits? In: AHS 2006. Proc. of the First NASA/ESA Conference on Adaptive Hardware and Systems, pp. 171–178. IEEE Computer Society Press, Los Alamitos (2006)Google Scholar
  10. 10.
    Gordon, V.S., Whitley, D.: Serial and Parallel Genetic Algorithms as Function Optimizers. In: Proc. of the Fifth International Conference on Genetic Algorithms, pp. 177–183. Morgan Kaufmann, San Mateo, CA (1993)Google Scholar
  11. 11.
    Cantu-Paz, E.: A Survey of Parallel Genetic Algorithms. Calculateurs Parallels 10(2), 141–171 (1998)Google Scholar
  12. 12.
    Coello Coello, C.A., Aguirre, A.H.: Design of Combinational Logic Circuits Through an Evolutionary Multiobjective Optimization Approach. Artificial Intelligence for Engineering, Design, Analysis and Manufacture 16(1), 39–53 (2002)Google Scholar
  13. 13.
    Potter, M.A., De Jong, K.A.: Cooperative Co-evolution: An Architecture for Evolving Coadapted Subcomponents. Evolutionary Computation 8(1), 1–29 (2000)CrossRefGoogle Scholar
  14. 14.
    Kalganova, T.: Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware. In: Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, pp. 65–74. IEEE Computer Society Press, Los Alamitos (2000)CrossRefGoogle Scholar
  15. 15.
    Sekanina, L., et al.: An Evolvable Combinational Unit for FPGAs. Computing and Informatics 23(5), 461–486 (2004)zbMATHGoogle Scholar
  16. 16.
    Miller, J.F., Thomson, P.: Cartesian Genetic Programming. In: Poli, R., Banzhaf, W., Langdon, W.B., Miller, J., Nordin, P., Fogarty, T.C. (eds.) EuroGP 2000. LNCS, vol. 1802, pp. 121–132. Springer, Heidelberg (2000)Google Scholar
  17. 17.
    Celoxica Inc., RC1000 Hardware Reference Manual V2.3 (2001)Google Scholar
  18. 18.
  19. 19.
    Martin, P.: A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C. Genetic Programming and Evolvable Machines 2(4), 317–343 (2001)zbMATHCrossRefGoogle Scholar
  20. 20.
    Bensaali, F., et al.: Accelerating Matrix Product on Reconfigurable Hardware for Image Processing Applications. IEE proceedings-Circuits, Devices and Systems 152(3), 236–246 (2005)CrossRefGoogle Scholar
  21. 21.
    Wolfram, S.: Universality and Complexity in Cellular Automata. Physica 10D, 1–35 (1984)MathSciNetGoogle Scholar
  22. 22.
    Miller, J.F., et al.: Principles in the Evolutionary Design of Digital Circuits–Part I. Journal of Genetic Programming and Evolvable Machines 1(1), 7–35 (2000)zbMATHCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Jin Wang
    • 1
  • Chang Hao Piao
    • 2
  • Chong Ho Lee
    • 1
  1. 1.Department of Information & Communication Engineering, Inha University, IncheonKorea
  2. 2.Department of Automation Engineering, ChongQing University of Posts and Telecommunications, ChongqingChina

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