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Evolving and Analysing “Useful” Redundant Logic

  • Asbjoern Djupdal
  • Pauline C. Haddow
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4684)

Abstract

Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to the creation of novel redundancy structures which may be applied to meet this challenge. An experimental setup and results for creating “useful” redundant structures is presented.

Keywords

Truth Table Circuit Output Cartesian Genetic Programming Redundant Structure Functional Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Asbjoern Djupdal
    • 1
  • Pauline C. Haddow
    • 1
  1. 1.CRAB Lab, Department of Computer and Information Science, Norwegian University of Science and Technology 

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