Abstract
Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to the creation of novel redundancy structures which may be applied to meet this challenge. An experimental setup and results for creating “useful” redundant structures is presented.
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Djupdal, A., Haddow, P.C. (2007). Evolving and Analysing “Useful” Redundant Logic. In: Kang, L., Liu, Y., Zeng, S. (eds) Evolvable Systems: From Biology to Hardware. ICES 2007. Lecture Notes in Computer Science, vol 4684. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74626-3_24
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DOI: https://doi.org/10.1007/978-3-540-74626-3_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74625-6
Online ISBN: 978-3-540-74626-3
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