Advertisement

Evolution of Polymorphic Self-checking Circuits

  • Lukas Sekanina
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4684)

Abstract

This paper presents elementary circuit components which exhibit self-checking properties; however, which do not utilize any additional signals to indicate the fault. The fault is indicated by generating specific values at some of standard outputs of a given circuit. In particular, various evolved adders containing conventional as well as polymorphic gates are proposed with less than duplication overhead which are able to detect a reasonable number of stuck-at-faults by oscillations at the carry-out output when the control signal of polymorphic gates oscillates.

Keywords

IEEE Computer Society Test Vector Fault Coverage Cartesian Genetic Programming Concurrent Error Detection 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Garvie, M.: Reliable Electronics through Artificial Evolution. PhD thesis, University of Sussex (2005)Google Scholar
  2. 2.
    Frank, M.: Reversibility for Efficient Computing. PhD thesis, Massachusetts Institute of Technology (1999)Google Scholar
  3. 3.
    Stoica, A., Zebulum, R.S., Keymeulen, D.: Polymorphic electronics. In: Liu, Y., Tanaka, K., Iwata, M., Higuchi, T., Yasunaga, M. (eds.) ICES 2001. LNCS, vol. 2210, pp. 291–302. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  4. 4.
    Stoica, A., Zebulum, R.S., Keymeulen, D., Lohn, J.: On polymorphic circuits and their design using evolutionary algorithms. In: Proc. of IASTED International Conference on Applied Informatics AI 2002, Insbruck, Austria (2002)Google Scholar
  5. 5.
    Zebulum, R.S., Stoica, A.: Multifunctional Logic Gates for Built-In Self-Testing. NASA Tech Briefs 30(3), 10 (2006)Google Scholar
  6. 6.
    Novak, O., Gramatova, E., Ubar, R.: Handbook of Testing Electronic Systems. Czech Technical University Publishing House (2005)Google Scholar
  7. 7.
    Pradhan, D.K.: Fault-Tolerant Computer System Design. Prentice-Hall, Englewood Cliffs (1996)Google Scholar
  8. 8.
    Diaz, M., Azéma, P., Ayache, J.M.: Unified design of self-checking and fail-safe combinational circuits and sequential machines. IEEE Trans. Computers 28(3), 276–281 (1979)zbMATHCrossRefGoogle Scholar
  9. 9.
    Piestrak, S.J.: Feasibility study of designing tsc sequential circuits with 100% fault coverage. In: 17th IEEE Int. Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 354–364. IEEE Computer Society Press, Los Alamitos (2002)Google Scholar
  10. 10.
    Touba, N.A., McCluskey, E.J.: Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7), 783–789 (1997)CrossRefGoogle Scholar
  11. 11.
    Marienfeld, D., Ocheretnij, V., Gössel, M., Sogomonyan, E.S.: Partially duplicated code-disjoint carry-skip adder. In: Proc. of the 17th IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 78–86. IEEE Computer Society Press, Los Alamitos (2002)Google Scholar
  12. 12.
    Kakaroudas, A.P., Papadomanolakis, K., Kokkinos, V., Goutis, C.E.: Comparative study on self-checking carry-propagate adders in terms of area, power and performance. In: Soudris, D.J., Pirsch, P., Barke, E. (eds.) PATMOS 2000. LNCS, vol. 1918, pp. 187–194. Springer, Heidelberg (2000)Google Scholar
  13. 13.
    Stoica, A., Zebulum, R., Guo, X., Keymeulen, D., Ferguson, I., Duong, V.: Taking Evolutionary Circuit Design From Experimentation to Implementation: Some Useful Techniques and a Silicon Demonstration. IEE Proc.-Comp. Digit. Tech. 151(4), 295–300 (2004)CrossRefGoogle Scholar
  14. 14.
    Zebulum, R.S., Stoica, A.: Four-Function Logic Gate Controlled by Analog Voltage. NASA Tech Briefs 30(3), 8 (2006)Google Scholar
  15. 15.
    Sekanina, L., Starecek, L., Gajda, Z., Kotasek, Z.: Evolution of multifunctional combinational modules controlled by the power supply voltage. In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, pp. 186–193. IEEE Computer Society Press, Los Alamitos (2006)CrossRefGoogle Scholar
  16. 16.
    Weste, N., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edn. Addison-Wesley, Reading (2004)Google Scholar
  17. 17.
    Wakerly, J.: Digital Design: Principles and Practices. Prentice-Hall, Englewood Cliffs (2000)Google Scholar
  18. 18.
    Miller, J., Job, D., Vassilev, V.: Principles in the Evolutionary Design of Digital Circuits – Part I. Genetic Programming and Evolvable Machines 1(1), 8–35 (2000)CrossRefGoogle Scholar
  19. 19.
    Sekanina, L.: Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. In: Proc. of the 10th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, pp. 1–4. IEEE Computer Society Press, Los Alamitos (2007)CrossRefGoogle Scholar
  20. 20.
    Ocheretnij, V., Marienfeld, D., Sogomonyan, E.S., Gössel, M.: Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits. In: 10th IEEE Int. On-Line Testing Symposium, pp. 31–36. IEEE Computer Society Press, Los Alamitos (2004)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Lukas Sekanina
    • 1
  1. 1.Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66 BrnoCzech Republic

Personalised recommendations