Advertisement

Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit

  • Min Xie
  • Youren Wang
  • Li Wang
  • Yuan Zhang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4684)

Abstract

Due to the generic and highly programmable nature, gate-based FPGA provides the ability to implement a wide range of application. However, its small cell and complex interconnection network cause problems of low hardware resource utilization ratio and long interconnection time-delay in compute-intensive information processing field. PMAC (Programmable Multiply-Add Cell) presented in this article ensures high-speed and flexibility by adding much programmability to the multiply-add structure. PMAC array architecture resolves these problems and greatly increases resource utilization ratio and the efficiency of information processing. By establishing PMAC model and simulating, PMAC array is actualized on the VirtexII Pro series XC2VP100 device. By implementing FFT butterfly operation and 4 th order FIR on PMAC array, flexibility and correctness of the architecture are proved. The results have also shown to have an average increase of 28.3% in resource utilization ratio and decrease of 15.5% in interconnection time-delay.

Keywords

Reconfigurable computing Reconfigurable hardware FPGA Operator-based programmable cell circuit Information processing 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Kuon, I., Rose, J.: Measuring the gap between FPGAs and ASICs. In: ACM/SIGDA 14th international symposium on Field programmable gate arrays, pp. 21–30 (2006)Google Scholar
  2. 2.
    Gao, H.: Study on Design Techniques of a SRAM-Based Field Programmable Gate Array (in Chinese), pp. 20–26. Xidian University, Xi’an (2005)Google Scholar
  3. 3.
    Signh, H., et al.: Morphosys: An Integrated Reconfigurable System for Data-Parallel and Communication-Intensive Application. IEEE Transaction on Computers 49(5), 465–481 (2000)CrossRefGoogle Scholar
  4. 4.
    Komuro, T., Ishii, I., Ishikawa, M., Yoshida, A.: A digital vision chip specialized for high-speed target tracking. IEEE Transactions on Electron Devices 50(1), 191–199 (2003)CrossRefGoogle Scholar
  5. 5.
    Galanis, M.D.: A Reconfigurable Coarse-Grain Data-Path for Accelerating Computational Intensive Kernels. Circuits, Systems and Computers 14(9), 887–893 (2005)Google Scholar
  6. 6.
    Ebeling, C., Cronquist, D.C., Franklin, P.: RaPiD-reconfigurable pipeline datapath. In: The 6th International Workshop in Field-Programmable Logic and applications, pp. 126–135 (1996)Google Scholar
  7. 7.
    Higuchi, T., Murakawa, M., Iwata, M., Kajitani, I., Wenxin Liu, I., et al.: Evolvable hardware at function level. In: Proceedings of IEEE International Conference on Evolutionary Computation, pp. 187–192 (1997)Google Scholar
  8. 8.
    Wu, H., Zhang, L.: Design of a novel Reconfigurable Multiplier (in Chinese). Microelectronics & Computer 21(9), 161–163 (2004)Google Scholar
  9. 9.
    Huang, Z.-j., Zhou, F., Tong, J.-r., et al.: A new FPGA logic block suitable for datapath circuits (in Chinese). Computer Engineering and Design 21(3), 29–34 (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Min Xie
    • 1
  • Youren Wang
    • 1
  • Li Wang
    • 1
  • Yuan Zhang
    • 1
  1. 1.College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics, 210016 NanjingChina

Personalised recommendations