Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit
Due to the generic and highly programmable nature, gate-based FPGA provides the ability to implement a wide range of application. However, its small cell and complex interconnection network cause problems of low hardware resource utilization ratio and long interconnection time-delay in compute-intensive information processing field. PMAC (Programmable Multiply-Add Cell) presented in this article ensures high-speed and flexibility by adding much programmability to the multiply-add structure. PMAC array architecture resolves these problems and greatly increases resource utilization ratio and the efficiency of information processing. By establishing PMAC model and simulating, PMAC array is actualized on the VirtexII Pro series XC2VP100 device. By implementing FFT butterfly operation and 4 th order FIR on PMAC array, flexibility and correctness of the architecture are proved. The results have also shown to have an average increase of 28.3% in resource utilization ratio and decrease of 15.5% in interconnection time-delay.
KeywordsReconfigurable computing Reconfigurable hardware FPGA Operator-based programmable cell circuit Information processing
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