Abstract
This paper discusses a large number of logic circuit mapping methods for complex systems, focusing on network hardware system designs. This logic mapping technique enables significant logic simulation time savings by mapping identical logic processor modules. Under the logic mapping method which is called the time division multiplexing (TDM) logic mapping method, the speed of the required to simulate it is significantly reduced, compared with conventional mapping methods, when folding the identical modules into a single module copy is done at the hardware description language (HDL) level. In principle, this method can be applied to any type of a network design platform, e.g., communication data stream through physical channel (fiber optic line), video signal transfer logic display environment, etc. In this paper, we demonstrate this method using several configurations of the IBM Serial Link architecture.
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Jeong, T. et al. (2007). A Time Division Multiplexing (TDM) Logic Mapping Method for Computational Applications. In: Gervasi, O., Gavrilova, M.L. (eds) Computational Science and Its Applications – ICCSA 2007. ICCSA 2007. Lecture Notes in Computer Science, vol 4705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74472-6_91
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DOI: https://doi.org/10.1007/978-3-540-74472-6_91
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