Abstract
Most of the mobile devices are equipped with NAND flash memories even if it has characteristics of not-in-place update and asymmetric I/O latencies among read, write, and erase operations: a write/erase operation is much slower than a read operation in a flash memory. For the overall performance of a flash memory system, the buffer replacement policy should consider the above severely asymmetric I/O latencies. Existing buffer replacement algorithms such as LRU, LIRS, and ARC cannot deal with the above problems. This paper proposes an add-on buffer replacement policy that enhances LIRS by reordering writes of not-cold dirty pages from the buffer cache to flash storage. The enhances LIRS-WSR algorithm focuses on reducing the number of write/erase operations as well as preventing serious degradation of buffer hit ratio. The trace-driven simulation results show that, among the existing buffer replacement algorithms including LRU, CF-LRU, ARC, and LIRS, our LIRS-WSR is best in almost cases for flash storage systems.
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Jung, H., Yoon, K., Shim, H., Park, S., Kang, S., Cha, J. (2007). LIRS-WSR: Integration of LIRS and Writes Sequence Reordering for Flash Memory. In: Gervasi, O., Gavrilova, M.L. (eds) Computational Science and Its Applications – ICCSA 2007. ICCSA 2007. Lecture Notes in Computer Science, vol 4705. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74472-6_18
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DOI: https://doi.org/10.1007/978-3-540-74472-6_18
Publisher Name: Springer, Berlin, Heidelberg
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