Abstract
Parallelism is now a central concern for architecture designers and compiler writers. Instruction-level parallelism and increasingly multi-cores are present in all contemporary processors. Furthermore, we are witnessing a convergence of interests with architects and compiler writers addressing large scale parallel machines, general-purpose platforms and specialised hardware designs such as graphic coprocessors or low-power embedded systems. Modern systems require system software and hardware to be designed in tandem, hence this topic is concerned with architecture design and compilation. Twenty-four papers were submitted to the track of which five were accepted split over two sessions.
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Keywords
- Hyperspectral Image
- Transactional Memory
- Chip Multiprocessor
- Transactional Memory System
- Data Compression Technique
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© 2007 Springer-Verlag Berlin Heidelberg
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O’Boyle, M., Bodin, F., Gonzalez, J., Vintan, L. (2007). Topic 4 High-Performance Architectures and Compilers. In: Kermarrec, AM., Bougé, L., Priol, T. (eds) Euro-Par 2007 Parallel Processing. Euro-Par 2007. Lecture Notes in Computer Science, vol 4641. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74466-5_26
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DOI: https://doi.org/10.1007/978-3-540-74466-5_26
Publisher Name: Springer, Berlin, Heidelberg
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